A low jitter clocking strategy for a 7.5-Gb/s SerDes array in 65nm CMOS technology. - Paul Madeira; Marc-Andre LaCroix; John Hogeboom (ESSCIRC, 2007)

A 112Gb/s PAM-4, 168Gb/s PAM-8 7bit DAC-Based Transmitter in 7nm FinFET. - Euhan Chong; Faisal Ahmed Musa; Ahmed N. Mustafa; Tim Gao; Peter Krotnev; Rashid Soreefan; Qian Xin; Paul Madeira; Davide Tonietto (ESSCIRC, 2021)

106 Gb/s PAM-4 Transmitter With 2.1 Vppd Swing in 7nm FinFET Process. - Hassan Sepehrian; Stephen Alie; Paul Madeira; Davide Tonietto (VLSI Circuits, 2021)