Strassen's matrix multiplication for customisable processors. - Henry M. D. Ip; James D. Low; Peter Y. K. Cheung; George A. Constantinides; Wayne Luk; Shay Ping Seng; Paul Metzgen (FPT, 2002)

A high performance 32-bit ALU for programmable logic. - Paul Metzgen (FPGA, 2004)

Optimizing a high performance 32-bit processor for programmable logic. - Paul Metzgen (SoC, 2004)

Multiplexer restructuring for FPGA implementation cost reduction. - Paul Metzgen; Dominic Nancekievill (DAC, 2005)

Cell Based Motion Estimators for Reconfigurable Platforms. - Wim J. C. Melis; Kieron Turkington; Alexander Whitton; Wayne Luk; Peter Y. K. Cheung; Paul Metzgen (ERSA, 2005)