Design and implementation of the POWER5 microprocessor. - Joachim G. Clabes; Joshua Friedrich; Mark Sweet; Jack DiLullo; Sam G. Chu; Donald W. Plass; James Dawson; Paul Muench; Larry Powell; Michael S. Floyd; Balaram Sinharoy; Mike Lee; et al. (DAC, 2004)

A Fault-Tolerant Middleware Architecture for High-Availability Storage Services. - Sangeetha Seshadri; Ling Liu 001; Brian F. Cooper; Lawrence Chiu; Karan Gupta; Paul Muench (IEEE SCC, 2007)

Enhancing Storage System Availability on Multi-Core Architectures with Recovery-Conscious Scheduling. - Sangeetha Seshadri; Lawrence Chiu; Cornel Constantinescu; Subashini Balachandran; Clem Dickey; Ling Liu 001; Paul Muench (FAST, 2008)

Optical Diagnostics for IBM POWER6- Microprocessor. - Peilin Song; Stephen Ippolito; Franco Stellari; John Sylvestri; Tim Diemoz; George Smith; Paul Muench; Norm James; Seongwon Kim; Hector Saenz (ITC, 2008)

Automated lookahead data migration in SSD-enabled multi-tiered storage systems. - Gong Zhang 008; Lawrence Chiu; Clem Dickey; Ling Liu 001; Paul Muench; Sangeetha Seshadri (MSST, 2010)

5.2 Distributed system of digitally controlled microregulators enabling per-core DVFS for the POWER8TM microprocessor. - Zeynep Toprak Deniz; Michael A. Sperling; John F. Bulzacchelli; Gregory S. Still; Ryan Kruse; Seongwon Kim; David Boerstler; Tilman Gloekler; Raphael Robertazzi; Kevin Stawiasz; Tim Diemoz; George English; et al. (ISSCC, 2014)

How Could a Flash Cache Degrade Database Performance Rather Than Improve It? Lessons to be Learnt from Multi-Tiered Storage. - Hyojun Kim; Ioannis Koltsidas; Nikolas Ioannou; Sangeetha Seshadri; Paul Muench; Clement L. Dickey; Lawrence Chiu (INFLOW, 2014)

Flash-Conscious Cache Population for Enterprise Database Workloads. - Hyojun Kim; Ioannis Koltsidas; Nikolas Ioannou; Sangeetha Seshadri; Paul Muench; Clement L. Dickey; Lawrence Chiu (ADMS@VLDB, 2014)

Software defined just-in-time caching in an enterprise storage system. - Sangeetha Seshadri; Paul Muench; Lawrence Chiu; Ioannis Koltsidas; Nikolas Ioannou; Robert Haas 001; Yang Liu; Mei Mei; Stephen Blinick (IBM J. Res. Dev., 2014)

The 12-Core POWER8™ Processor With 7.6 Tb/s IO Bandwidth, Integrated Voltage Regulation, and Resonant Clocking. - Eric J. Fluhr; Steve Baumgartner; David W. Boerstler; John F. Bulzacchelli; Timothy Diemoz; Daniel Dreps; George English; Joshua Friedrich; Anne Gattiker; Tilman Gloekler; Christopher J. Gonzalez; Jason Hibbeler; et al. (IEEE J. Solid State Circuits, 2015)

Trillion Operations Key-Value Storage Engine: Revisiting the Mission Critical Analytics Storage Software Stack. - Sangeetha Seshadri; Paul Muench; Lawrence Chiu (ICDCS, 2017)

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. - Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy Diemoz; Pierce Chuang; Christos Vezyrtzis (ISSCC, 2017)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

Reliability of Centralized vs. Parallel Software Models for Composable Storage Systems. - Mario Blaum; Paul Muench (QRS, 2021)

AIOps Essential to Unified Resiliency Management in Data Lakehouses. - Runyu Jin; Paul Muench; Veera Deenadhayalan; Brian Hatfield (IEEE Big Data, 2022)

Baking Disaster-Proof Kubernetes Applications with Efficient Recipes. - Runyu Jin; Paul Muench; Travis Janssen; Brian Hatfield; Veera Deenadhayalan (ICPE (Companion), 2024)

The infrastructure powering IBM's Gen AI model development. - Talia Gershon; Seetharami Seelam; Brian Belgodere; Milton Bonilla; Lan Hoang; Danny Barnett; I-Hsin Chung; Apoorve Mohan; Ming-Hung Chen; Lixiang Luo; Robert Walkup; Constantinos Evangelinos; et al. (CoRR, 2024)