Integrated circuits for local digital switching line interfaces. - Paul R. Gray; David G. Messerschmitt (IEEE Commun. Mag., 1980)

Automatic layout generation for CMOS operational amplifiers. - Han Young Koh; Carlo H. Séquin; Paul R. Gray (ICCAD, 1988)

A positive-feedback transconductance amplifier with applications to high-frequency, high-Q CMOS switched-capacitor filters. - Carlos A. Laber; Paul R. Gray (IEEE J. Solid State Circuits, 1988)

Area-efficient multichannel oversampled PCM voice-band coder. - Bosco H. Leung; Robert R. Neff; Paul R. Gray; Robert W. Brodersen (IEEE J. Solid State Circuits, 1988)

A pipelined 13-bit 250-ks/s 5-V analog-to-digital converter. - Sehat Sutarja; Paul R. Gray (IEEE J. Solid State Circuits, 1988)

A scalable switched-capacitor filter implemented in 1.25- mu m technology. - Sui-Ping Shieh; Chorng-Kuang Wang; Rinaldo Castello; Paul R. Gray (IEEE J. Solid State Circuits, 1989)

A 10-bit 5-Msample/s CMOS two-step flash ADC. - Joey Doernberg; Paul R. Gray; David A. Hodges (IEEE J. Solid State Circuits, 1989)

CADICS - Cyclic Analog-to-Digital Converter Synthesis. - Gani Jusuf; Paul R. Gray; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

OPASYN: a compiler for CMOS operational amplifiers. - Han Young Koh; Carlo H. Séquin; Paul R. Gray (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990)

A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOS. - Beomsup Kim; David N. Helman; Paul R. Gray (IEEE J. Solid State Circuits, 1990)

A Behavioral Representation for Nyquist Rate A/D Converters. - Edward W. Y. Liu; Alberto L. Sangiovanni-Vincentelli; Georges G. E. Gielen; Paul R. Gray (ICCAD, 1991)

A 13-b 2.5-MHz self-calibrated pipelined A/D converter in 3- mu m CMOS. - Yuh-Min Lin; Beomsup Kim; Paul R. Gray (IEEE J. Solid State Circuits, 1991)

An 8-b 85-MS/s parallel pipeline A/D converter in 1- mu m CMOS. - Cormac S. G. Conroy; David W. Cline; Paul R. Gray (IEEE J. Solid State Circuits, 1993)

A 20-MHz sixth-order BiCMOS parasitic-insensitive continuous-time filter and second-order equalizer optimized for disk-drive read channels. - Carlos A. Laber; Paul R. Gray (IEEE J. Solid State Circuits, 1993)

A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2- mu m CMOS. - Timothy H. Hu; Paul R. Gray (IEEE J. Solid State Circuits, 1993)

A monolithic analog video comb filter in 1.2- mu m CMOS. - Ken A. Nishimura; Paul R. Gray (IEEE J. Solid State Circuits, 1993)

PLL/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design. - Beomsup Kim; Todd C. Weigandt; Paul R. Gray (ISCAS, 1994)

Analysis of Timing Jitter in CMOS Ring Oscillators. - Todd C. Weigandt; Beomsup Kim; Paul R. Gray (ISCAS, 1994)

A 100 MHz A/D interface for PRML magnetic disk read channels. - Gregory T. Uehara; Paul R. Gray (IEEE J. Solid State Circuits, 1994)

A 10 b, 20 Msample/s, 35 mW pipeline A/D converter. - Thomas Byunghak Cho; Paul R. Gray (IEEE J. Solid State Circuits, 1995)

A 50 MHz eight-tap adaptive equalizer for partial-response channels. - Caesar S. H. Wong; Jacques C. Rudell; Gregory T. Uehara; Paul R. Gray (IEEE J. Solid State Circuits, 1995)

A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS. - David W. Cline; Paul R. Gray (IEEE J. Solid State Circuits, 1996)

A module generator for high-speed CMOS current output digital/analog converters. - Robert R. Neff; Paul R. Gray; Alberto L. Sangiovanni-Vincentelli (IEEE J. Solid State Circuits, 1996)

A 1.9-GHz wide-band IF double conversion CMOS receiver for cordless telephone applications. - Jacques C. Rudell; Jia-Jiunn Ou; Thomas Byunghak Cho; George Chien; Francesco Brianti; Jeffrey A. Weldon; Paul R. Gray (IEEE J. Solid State Circuits, 1997)

A 13 bit, 1.4 MS/s, 3.3 V sigma-delta modulator for RF baseband channel applications. - Arnold R. Feldman; Bernhard E. Boser; Paul R. Gray (CICC, 1998)

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems. - Jacques Christophe Rudell; Jia-Jiunn Ou; R. Sekhar Narayanaswami; George Chien; Jeffrey A. Weldon; Li Lin 009; King-Chun Tsai; Luns Tee; Kelvin Khoo; Danelle Au; Troy Robinson; Danilo Gerna; et al. (ISLPED, 1998)

A 13-bit, 1.4-MS/s sigma-delta modulator for RF baseband channel applications. - Arnold R. Feldman; Bernhard E. Boser; Paul R. Gray (IEEE J. Solid State Circuits, 1998)

A 75-mW 128-MHz DS-CDMA baseband demodulator for high-speed wireless applications [LANs]. - Keith K. Onodera; Paul R. Gray (IEEE J. Solid State Circuits, 1998)

A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter. - Andrew M. Abo; Paul R. Gray (IEEE J. Solid State Circuits, 1999)

A 1.9-GHz, 1-W CMOS class-E power amplifier for wireless communications. - King-Chun Tsai; Paul R. Gray (IEEE J. Solid State Circuits, 1999)

A 900-MHz local oscillator using a DLL-based frequency multiplier technique for PCS applications. - George Chien; Paul R. Gray (IEEE J. Solid State Circuits, 2000)

A 1.75-GHz highly integrated narrow-band CMOS transmitter with harmonic-rejection mixers. - Jeffrey A. Weldon; R. Sekhar Narayanaswami; Jacques Christophe Rudell; Li Lin 009; Masanori Otsuka; Sébastien Dedieu; Luns Tee; King-Chun Tsai; Cheol-Woong Lee; Paul R. Gray (IEEE J. Solid State Circuits, 2001)

A 14-b 12-MS/s CMOS pipeline ADC with over 100-dB SFDR. - Yun Chiu; Paul R. Gray; Borivoje Nikolic (IEEE J. Solid State Circuits, 2004)

Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. - Yun Chiu; Cheongyuen W. Tsang; Borivoje Nikolic; Paul R. Gray (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Scaling of analog-to-digital converters into ultra-deep-submicron CMOS. - Yun Chiu; Borivoje Nikolic; Paul R. Gray (CICC, 2005)

A 1.7GHz 1.5W CMOS RF Doherty Power Amplifier for Wireless Communications. - Naratip Wongkomet; Luns Tee; Paul R. Gray (ISSCC, 2006)

A $+$31.5 dBm CMOS RF Doherty Power Amplifier for Wireless Communications. - Naratip Wongkomet; Luns Tee; Paul R. Gray (IEEE J. Solid State Circuits, 2006)