Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. - Patrick C. McGeer; Alexander Saldanha; Paul R. Stephan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1991)

Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications. - Cho W. Moon; Paul R. Stephan; Robert K. Brayton (ICCAD, 1991)

Physically Realizable Gate Models. - Paul R. Stephan; Robert K. Brayton (ICCD, 1993)

Specification, synthesis, and verification of hazard-free asynchronous circuits. - Cho W. Moon; Paul R. Stephan; Robert K. Brayton (J. VLSI Signal Process., 1994)

Combinational test generation using satisfiability. - Paul R. Stephan; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)