Three dimensional silicon integration using fine pitch interconnection, silicon processing and silicon carrier packaging technology. - John U. Knickerbocker; Chirag S. Patel; Paul S. Andry; Cornelia K. Tsang; L. Paivikki Buchwalter; Edmund J. Sprogis; Hua Gan; Raymond R. Horton; Robert J. Polastre; Steven L. Wright; Christian D. Schuster; Christian W. Baks; et al. (CICC, 2005)

Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection. - John U. Knickerbocker; Paul S. Andry; L. Paivikki Buchwalter; Alina Deutsch; Raymond R. Horton; Keith A. Jenkins; Young Hoon Kwark; Gerald McVicker; Chirag S. Patel; Robert J. Polastre; Christian D. Schuster; Arun Sharma; et al. (IBM J. Res. Dev., 2005)

3-D Silicon Integration and Silicon Packaging Technology Using Silicon Through-Vias. - John U. Knickerbocker; Chirag S. Patel; Paul S. Andry; Cornelia K. Tsang; L. Paivikki Buchwalter; Edmund J. Sprogis; Hua Gan; Raymond R. Horton; Robert J. Polastre; Steven L. Wright; John M. Cotte (IEEE J. Solid State Circuits, 2006)

Interconnects in the Third Dimension: Design Challenges for 3D ICs. - Kerry Bernstein; Paul S. Andry; Jerome Cann; Philip G. Emma; David Greenberg; Wilfried Haensch; Mike Ignatowski; Steven J. Koester; John Magerlein; Ruchir Puri; Albert M. Young (DAC, 2007)

Fabrication and characterization of robust through-silicon vias for silicon-carrier applications. - Paul S. Andry; Cornelia K. Tsang; Bucknell C. Webb; Edmund J. Sprogis; Steven L. Wright; Bing Dang; Dennis G. Manzer (IBM J. Res. Dev., 2008)

3D chip stacking with C4 technology. - Bing Dang; Steven L. Wright; Paul S. Andry; Edmund J. Sprogis; Cornelia K. Tsang; M. John Interrante; Bucknell C. Webb; Robert J. Polastre; Raymond R. Horton; Chirag S. Patel; Arun Sharma; J. Zheng; et al. (IBM J. Res. Dev., 2008)

Three-dimensional silicon integration. - John U. Knickerbocker; Paul S. Andry; Bing Dang; Raymond R. Horton; Mario J. Interrante; Chirag S. Patel; Robert J. Polastre; Katsuyuki Sakuma; Ranjani Sirdeshmukh; Edmund J. Sprogis; Sri M. Sri-Jayantha; Antonio M. Stephens; et al. (IBM J. Res. Dev., 2008)

3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections. - Katsuyuki Sakuma; Paul S. Andry; Cornelia K. Tsang; Steven L. Wright; Bing Dang; Chirag S. Patel; Bucknell C. Webb; J. Maria; Edmund J. Sprogis; S. K. Kang; Robert J. Polastre; Raymond R. Horton; et al. (IBM J. Res. Dev., 2008)

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects. - Timothy O. Dickson; Yong Liu 023; Sergey V. Rylov; Bing Dang; Cornelia K. Tsang; Paul S. Andry; John F. Bulzacchelli; Herschel A. Ainspan; Xiaoxiong Gu; Lavanya Turlapati; Michael P. Beakes; Benjamin D. Parker; et al. (IEEE J. Solid State Circuits, 2012)

An 82%-efficient multiphase voltage-regulator 3D interposer with on-chip magnetic inductors. - Kevin Tien; Noah Sturcken; Naigang Wang; Jae-Woong Nah; Bing Dang; Eugene J. O'Sullivan; Paul S. Andry; Michele Petracca; Luca P. Carloni; William J. Gallagher; Kenneth L. Shepard (VLSIC, 2015)