Artificial Intelligence in Purchasing: Facilitating Mechanism Design-based Negotiations. - Ines Schulze-Horn; Sabrina Hueren; Paul Scheffler; Holger Schiele (Appl. Artif. Intell., 2020)

Indirection Stream Semantic Register Architecture for Efficient Sparse-Dense Linear Algebra. - Paul Scheffler; Florian Zaruba; Fabian Schuiki; Torsten Hoefler; Luca Benini (DATE, 2021)

Banshee: A Fast LLVM-Based RISC-V Binary Translator. - Samuel Riedel; Fabian Schuiki; Paul Scheffler; Florian Zaruba; Luca Benini (ICCAD, 2021)

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters. - Gianna Paulin; Matheus A. Cavalcante; Paul Scheffler; Luca Bertaccini; Yichao Zhang 003; Frank K. Gürkaynak; Luca Benini (ISVLSI, 2022)

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads. - Chi Zhang; Paul Scheffler; Thomas Benz; Matteo Perotti; Luca Benini (DATE, 2023)

Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In. - Alessandro Ottaviano; Thomas Benz; Paul Scheffler; Luca Benini (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Sparse Stream Semantic Registers: A Lightweight ISA Extension Accelerating General Sparse Linear Algebra. - Paul Scheffler; Florian Zaruba; Fabian Schuiki; Torsten Hoefler; Luca Benini (IEEE Trans. Parallel Distributed Syst., 2023)

NARS: Neuromorphic Acceleration through Register-Streaming Extensions on RISC-V Cores. - Simone Manoni; Paul Scheffler; Alfio Di Mauro; Luca Zanatta; Andrea Acquaviva; Luca Benini; Andrea Bartolini (CF (Companion), 2024)

SARIS: Accelerating Stencil Computations on Energy-Efficient RISC-V Compute Clusters with Indirect Stream Registers. - Paul Scheffler; Luca Colagrande; Luca Benini (DAC, 2024)

Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV. - Chi Zhang; Paul Scheffler; Thomas Benz; Matteo Perotti; Luca Benini (DATE, 2024)

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET. - Gianna Paulin; Paul Scheffler; Thomas Benz; Matheus A. Cavalcante; Tim Fischer 001; Manuel Eggimann; Yichao Zhang 003; Nils Wistoff; Luca Bertaccini; Luca Colagrande; Gianmarco Ottavi; Frank K. Gürkaynak; et al. (VLSI Technology and Circuits, 2024)

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC. - Philippe Sauter; Thomas Benz; Paul Scheffler; Zerun Jiang; Beat Muheim; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

Insights from Basilisk: Are Open-Source EDA Tools Ready for a Multi-Million-Gate, Linux-Booting RV64 SoC Design? - Philippe Sauter; Thomas Benz; Paul Scheffler; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS. - Paul Scheffler; Philippe Sauter; Thomas Benz; Frank K. Gürkaynak; Luca Benini (CoRR, 2024)

A High-Performance, Energy-Efficient Modular DMA Engine Architecture. - Thomas Benz; Michael Rogenmoser; Paul Scheffler; Samuel Riedel; Alessandro Ottaviano; Andreas Kurth; Torsten Hoefler; Luca Benini (IEEE Trans. Computers, 2024)

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions. - Simone Manoni; Paul Scheffler; Luca Zanatta; Andrea Acquaviva; Luca Benini; Andrea Bartolini (DATE, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (CoRR, 2025)

ArtistIC: An Open-Source Toolchain for Top-Metal IC Art and Ultra-High-Fidelity GDSII Renders. - Thomas Benz; Paul Scheffler; Nils Wistoff; Philippe Sauter; Beat Muheim; Luca Benini (CoRR, 2025)

Croc: An End-to-End Open-Source Extensible RISC-V MCU Platform to Democratize Silicon. - Philippe Sauter; Thomas Benz; Paul Scheffler; Hannah Pochert; Luisa Wüthrich; Martin Poviser; Beat Muheim; Frank K. Gürkaynak; Luca Benini (CoRR, 2025)

A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications. - Angelo Garofalo; Alessandro Ottaviano; Matteo Perotti; Thomas Benz; Yvan Tortorella; Robert Balas; Michael Rogenmoser; Chi Zhang; Luca Bertaccini; Nils Wistoff; Maicol Ciani; Cyril Koenig; et al. (CoRR, 2025)

Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET. - Paul Scheffler; Thomas Benz; Viviane Potocnik; Tim Fischer 001; Luca Colagrande; Nils Wistoff; Yichao Zhang 003; Luca Bertaccini; Gianmarco Ottavi; Manuel Eggimann; Matheus A. Cavalcante; Gianna Paulin; et al. (IEEE J. Solid State Circuits, 2025)

Basilisk: A 34 mm2 End-to-End Open-Source 64-bit Linux-Capable RISC-V SoC in 130nm BiCMOS. - Philippe Sauter; Thomas Benz; Paul Scheffler; Martin Poviser; Frank K. Gürkaynak; Luca Benini (CoRR, 2025)