The binary floating point digital differential analyzer. - James L. Elshoff; Paul T. Hulina (AFIPS Fall Joint Computing Conference, 1970)

Elimination of Static and Dynamic Hazards in Combinatorial Switching Circuits - Jon G. Bredeson; Paul T. Hulina (SWAT, 1970)

On Tracey's Internal State Assignment Method. - Paul T. Hulina; Jon G. Bredeson (IEEE Trans. Computers, 1970)

Generation of a Clock Pulse for Asynchronous Sequential Machines to Eliminate Critical Races. - Jon G. Bredeson; Paul T. Hulina (IEEE Trans. Computers, 1971)

Generation of Prime Implicants by Direct Multiplication. - Jon G. Bredeson; Paul T. Hulina (IEEE Trans. Computers, 1971)

Elimination of Static and Dynamic Hazards for Multiple Input Changes in Combinatorial Switching Circuits - Jon G. Bredeson; Paul T. Hulina (Inf. Control., 1972)

Synthesis of Multiple-Input Change Asynchronous Circuits Using Transition-Sensitive Flip-Flops. - Jon G. Bredeson; Paul T. Hulina (IEEE Trans. Computers, 1973)

A Reconfigurable Multiprocessor. - Lee D. Coraor; Paul T. Hulina (ICPP, 1985)

A Hardware Memory Mapping Unit for Efficient Address Computation. - Paul T. Hulina; Lee D. Coraor (ICPP, 1987)

A General Model for Memory-Based Finite-State Machines. - Lee D. Coraor; Paul T. Hulina; Orlando A. Morean (IEEE Trans. Computers, 1987)

Coprocessor architectures for efficient address computation and memory accessing. - Paul T. Hulina; Lee D. Coraor (Comput. Syst. Sci. Eng., 1990)

Performance Analysis of an Address Generation Coprocessor. - Paul T. Hulina; Lee D. Coraor; Shih-Wei Sun (ICPP (1), 1991)

Classification and Performance Evaluation of Instruction Buffering Techniques. - Lizyamma Kurian; Paul T. Hulina; Lee D. Coraor; Dhamir N. Mannai (ISCA, 1991)

Memory Latency Effects in Decoupled Architectures With a Single Data Memory Module. - Lizyamma Kurian; Paul T. Hulina; Lee D. Coraor (ISCA, 1992)

Design and VLSI implementation of an access processor for a decoupled architecture. - Paul T. Hulina; Lizyamma Kurian; Eugene B. John; Lee D. Coraor (Microprocess. Microsystems, 1992)

Structured Data Access Mechanisms for a Decoupled Computer Architecture. - Ali Berrached; Paul T. Hulina; Lee D. Coraor (ICPP (2), 1994)

Module Partitioning and Interlaced Data Placement Schemes to Reduce Conflicts in Interleaved Memories. - Lizyamma Kurian; Bermjae Choi; Paul T. Hulina; Lee D. Coraor (ICPP (1), 1994)

Memory Latency Effects in Decoupled Architectures. - Lizyamma Kurian; Paul T. Hulina; Lee D. Coraor (IEEE Trans. Computers, 1994)

A comparative evaluation of software techniques to hide memory latency. - Lizy Kurian John; Vinod Reddy; Paul T. Hulina; Lee D. Coraor (HICSS (1), 1995)

Program Balance and Its Impact on High Performance RISC Architectures. - Lizy Kurian John; Vinod Reddy; Paul T. Hulina; Lee D. Coraor (HPCA, 1995)

An electronics manufacturing minor in engineering with emphasis on rapid prototyping. - Paul T. Hulina; David L. Landis (MSE, 1997)

A WWW facilitated rapid system prototyping class. - David L. Landis; Paul T. Hulina (MSE, 1997)

Evaluation of Computing in Memory Architectures for Digital Image Processing Applications. - David L. Landis; Paul T. Hulina; Scott Deno; Luke Roth; Lee D. Coraor (ICCD, 1999)

Computing in Memory Architectures for Digital Image Processing. - Luke Roth; Lee D. Coraor; David L. Landis; Paul T. Hulina; Scott Deno (MTDT, 1999)

A Rapid Prototyping Methodology for Reverse Engineering of Legacy Electronic Systems. - Scott Deno; David L. Landis; Paul T. Hulina; Sanjay Balasubramanian (IEEE International Workshop on Rapid System Prototyping, 1999)

Language-Based Rapid Prototyping Methods for Legacy System Re-Engineering and Re-Use. - David L. Landis; Praveen Guddeti; Paul T. Hulina; Lee D. Coraor (IEEE International Workshop on Rapid System Prototyping, 1999)