DARSI: RC data reduction [VLSI simulation]. - Paul Vanoostende; Paul Six; Hugo De Man (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991)

Estimation of typical power of synchronous CMOS circuits using a hierarchy of simulators. - Paul Vanoostende; Paul Six; Joos Vandewalle; Hugo J. De Man (IEEE J. Solid State Circuits, 1993)

Retargetable code generation: key issues for successful introduction. - Paul Vanoostende; Etienne Vanzieleghem; Emmanuel Rousseau; Christian Massy; François Gérard (Code Generation for Embedded Processors, 1994)

Design of a C-testable booth multiplier using a realistic fault model. - Jos van Sas; Chay Nowé; Didier Pollet; Francky Catthoor; Paul Vanoostende; Hugo De Man (J. Electron. Test., 1994)

Issues in low-power design for telecom. - Paul Vanoostende; Geert van Wauwe (EURO-DAC, 1995)

On the use of VHDL-based behavioral synthesis for telecom ASIC design. - Mark Genoe; Paul Vanoostende; Geert van Wauwe (ISSS, 1995)