A wire load model considering metal layer properties. - Armin Windschiegl; Torsten Mahnke; Michael Eiermann; Walter Stechele; Paul Zuber (ICECS, 2002)

Exploiting Metal Layer Characteristics for Low-Power Routing. - Armin Windschiegl; Paul Zuber; Walter Stechele (PATMOS, 2002)

Reduction of CMOS Power Consumption and Signal Integrity Issues by Routing Optimization. - Paul Zuber; Armin Windschiegl; Raúl Medina Beltrán de Otálora; Walter Stechele; Andreas Herkersdorf (DATE, 2005)

Optimization Potential of CMOS Power by Wire Spacing. - Paul Zuber; Florian Helmut Müller; Walter Stechele (GI Jahrestagung (1), 2005)

The Optimal Wire Order for Low Power CMOS. - Paul Zuber; Peter Gritzmann; Michael Ritter; Walter Stechele (PATMOS, 2005)

Variability aware modeling of SoCs: From device variations to manufactured system yield. - Miguel Miranda; Bart Dierickx; Paul Zuber; Petr Dobrovolný; F. Kutscherauer; Philippe Roussel; Pavel Poliakov (ISQED, 2009)

Exponent Monte Carlo for Quick Statistical Circuit Simulation. - Paul Zuber; Vladimir Matvejev; Philippe Roussel; Petr Dobrovolný; Miguel Miranda (PATMOS, 2009)

Wire Topology Optimization for Low Power CMOS. - Paul Zuber; Othman Bahlous; Thomas Ilnseher; Michael Ritter; Walter Stechele (IEEE Trans. Very Large Scale Integr. Syst., 2009)

A holistic approach for statistical SRAM analysis. - Paul Zuber; Petr Dobrovolný; Miguel Miranda (DAC, 2010)

Statistical SRAM analysis for yield enhancement. - Paul Zuber; Miguel Miranda; Petr Dobrovolný; Koen van der Zanden; Jong-Hoon Jung (DATE, 2010)

Optimal wire ordering and spacing in low power semiconductor design. - Peter Gritzmann; Michael Ritter; Paul Zuber (Math. Program., 2010)

Variability Aware Sub-Wavelength Lithography Characterization for Robust SRAM Design. - Petr Dobrovolný; Miguel Miranda; Paul Zuber (ARCS Workshops, 2011)

Variability aware modeling for yield enhancement of SRAM and logic. - Miguel Miranda; Paul Zuber; Petr Dobrovolný; Philippe Roussel (DATE, 2011)

New reliability mechanisms in memory design for sub-22nm technologies. - Nivard Aymerich; A. Asenov; Andrew R. Brown; Ramon Canal; Binjie Cheng; Joan Figueras; Antonio González 001; Enric Herrero; S. Markov; Miguel Miranda; Peyman Pouyan; Tanausú Ramírez; et al. (IOLTS, 2011)

TRAMS Project: Variability and Reliability of SRAM Memories in sub-22 nm Bulk-CMOS Technologies. - Ramon Canal; Antonio Rubio 001; A. Asenov; A. Brown; Miguel Miranda; Paul Zuber; Antonio González 001; Xavier Vera (FET, 2011)

Analysis of FinFET technology on memories. - Esteve Amat; A. Asenov; Ramon Canal; Binjie Cheng; J.-Ll. Cruz; Zoran Jaksic; Miguel Miranda; Antonio Rubio 001; Paul Zuber (IOLTS, 2012)

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes. - Arindam Mallik; Paul Zuber; Tsung-Te Liu; Bharani Chava; Bhavana Ballal; Pablo Royer Del Bario; Rogier Baert; Kris Croes; Julien Ryckaert; Mustafa Badaroglu; Abdelkarim Mercha; Diederik Verkest (DAC, 2013)