Prime Implicant Computation Using Satisfiability Algorithms. - Vasco M. Manquinho; Paulo F. Flores; João P. Marques Silva; Arlindo L. Oliveira (ICTAI, 1997)

On Applying Set Covering Models to Test Set Compaction. - Paulo F. Flores; Horácio C. Neto; João P. Marques Silva (Great Lakes Symposium on VLSI, 1999)

Test pattern generation for width compression in BIST. - Paulo F. Flores; Horácio C. Neto; Krishnendu Chakrabarty; João Marques-Silva 001 (ISCAS (1), 1999)

Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation. - Paulo F. Flores; José C. Costa; Horácio C. Neto; José Monteiro 001; João Marques-Silva 001 (VLSI Design, 1999)

An exact solution to the minimum size test pattern problem. - Paulo F. Flores; Horácio C. Neto; João P. Marques Silva (ACM Trans. Design Autom. Electr. Syst., 2001)

Maximal sharing of partial terms in MCM under minimal signed digit representation. - Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (ECCTD, 2005)

An exact algorithm for the maximal sharing of partial terms in multiple constant multiplications. - Paulo F. Flores; José Monteiro 001; Eduardo A. C. da Costa (ICCAD, 2005)

Optimization of area under a delay constraint in digital filter synthesis using SAT-based integer linear programming. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2006)

ASSUMEs: Heuristic Algorithms for Optimization of Area and Delay in Digital Filter Synthesis. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICECS, 2006)

Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. - Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (SBCCI, 2006)

Optimization of Area in Digital FIR Filters using Gate-Level Metrics. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (DAC, 2007)

Minimum number of operations under a general number representation for digital filter synthesis. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (ECCTD, 2007)

Effect of Number Representation on the Achievable Minimum Number of Operations in Multiple Constant Multiplications. - Levent Aksoy; Ece Olcay Günes; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (SiPS, 2007)

Application Specific Programmable IP Core for Motion Estimation: Technology Comparison Targeting Efficient Embedded Co-Processing Units. - Nuno Sebastião; Tiago Dias 001; Nuno Roma; Paulo F. Flores; Leonel Sousa (DSD, 2008)

Generating Worst-Case Stimuli for Accurate Power Grid Analysis. - Pedro Marques Morgado; Paulo F. Flores; José C. Monteiro 001; Luís Miguel Silveira (PATMOS, 2008)

Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

PMSat: a parallel version of MiniSAT. - Luís Gil; Paulo F. Flores; Luís Miguel Silveira (J. Satisf. Boolean Model. Comput., 2009)

Generating realistic stimuli for accurate power grid analysis. - Pedro Marques Morgado; Paulo F. Flores; L. Miguel Silveira (ACM Trans. Design Autom. Electr. Syst., 2009)

A new quaternary FPGA based on a voltage-mode multi-valued circuit. - Cristiano Lazzari; Paulo F. Flores; José Monteiro 001; Luigi Carro (DATE, 2010)

Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DSD, 2010)

Integrated accelerator architecture for DNA sequences alignment with enhanced traceback phase. - Nuno Sebastião; Tiago Dias 001; Nuno Roma; Paulo F. Flores (HPCS, 2010)

Voltage-mode quaternary FPGAs: An evaluation of interconnections. - Cristiano Lazzari; Paulo F. Flores; José Monteiro 001; Luigi Carro (ISCAS, 2010)

An Efficient Low Power Multiple-Value Look-Up Table Targeting Quaternary FPGAs. - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (PATMOS, 2010)

Design of low-complexity and high-speed digital Finite Impulse Response filters. - Diego Jaccottet; Eduardo Costa 001; Levent Aksoy; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2010)

Search algorithms for the multiple constant multiplications problem: Exact and approximate. - Levent Aksoy; Ece Olcay Günes; Paulo F. Flores (Microprocess. Microsystems, 2010)

Optimization of gate-level area in high throughput Multiple Constant Multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2011)

Design of low-power multiple constant multiplications using low-complexity minimum depth operations. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Efficient shift-adds design of digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2011)

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ISCAS, 2011)

A hybrid algorithm for the optimization of area and delay in linear DSP transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2011)

Multiplierless Design of Linear DSP Transforms. - Levent Aksoy; Eduardo A. C. da Costa; Paulo F. Flores; José Monteiro 001 (VLSI-SoC (Selected Papers), 2011)

Low Power Multiple-Value Voltage-Mode Look-Up Table for Quaternary Field Programmable Gate Arrays. - Cristiano Lazzari; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (J. Low Power Electron., 2011)

Finding the optimal tradeoff between area and delay in multiple constant multiplications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Microprocess. Microsystems, 2011)

Design of low-complexity digital finite impulse response filters on FPGAs. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (DATE, 2012)

Multiple tunable constant multiplications: Algorithms and applications. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ICCAD, 2012)

Design and characterization of a QLUT in a standard CMOS process. - Diogo Brito; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (ICECS, 2012)

High-level algorithms for the optimization of gate-level area in digit-serial multiple constant multiplications. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (Integr., 2012)

Hardware accelerator architecture for simultaneous short-read DNA sequences alignment with enhanced traceback phase. - Nuno Sebastião; Nuno Roma; Paulo F. Flores (Microprocess. Microsystems, 2012)

Optimization Algorithms for the Multiplierless Realization of Linear Transforms. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2012)

Integrated Hardware Architecture for Efficient Computation of the $n$-Best Bio-Sequence Local Alignments in Embedded Platforms. - Nuno Sebastião; Nuno Roma; Paulo F. Flores (IEEE Trans. Very Large Scale Integr. Syst., 2012)

BioBlaze: Multi-core SIMD ASIP for DNA sequence alignment. - Nuno Neves 002; Nuno Sebastião; Andre Patricio; David Martins de Matos; Pedro Tomás; Paulo F. Flores; Nuno Roma (ASAP, 2013)

Exploration of tradeoffs in the design of integer cosine transforms for image compression. - Levent Aksoy; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (ECCTD, 2013)

Improving SAT Solver Efficiency Using a Multi-Core Approach. - Ricardo Marques; Luis G. Silva; Paulo F. Flores; L. Miguel Silveira (FLAIRS, 2013)

SIREN: a depth-first search algorithm for the filter design optimization problem. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ACM Great Lakes Symposium on VLSI, 2013)

Standard CMOS voltage-mode QLUT using a clock boosting technique. - Diogo Brito; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (NEWCAS, 2013)

Towards the least complex time-multiplexed constant multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (VLSI-SoC, 2013)

Configurable and scalable class of high performance hardware accelerators for simultaneous DNA sequence alignment. - Nuno Sebastião; Nuno Roma; Paulo F. Flores (Concurr. Comput. Pract. Exp., 2013)

Design of Digit-Serial FIR Filters: Algorithms, Architectures, and a CAD Tool. - Levent Aksoy; Cristiano Lazzari; Eduardo Costa 001; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Optimization of design complexity in time-multiplexed constant multiplications. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (DATE, 2014)

Optimized ASIP architecture for compressed BWT-indexed search in bioinformatics applications. - Nuno Sebastião; Paulo F. Flores; Nuno Roma (HPCS, 2014)

Efficient design of FIR filters using hybrid multiple constant multiplications on FPGA. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ICCD, 2014)

ECHO: A novel method for the multiplierless design of constant array vector multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ISCAS, 2014)

A Tutorial on Multiplierless Design of FIR Filters: Algorithms and Architectures. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (Circuits Syst. Signal Process., 2014)

Multiplierless Design of Folded DSP Blocks. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ACM Trans. Design Autom. Electr. Syst., 2014)

Approximation of multiple constant multiplications using minimum look-up tables on FPGA. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (ISCAS, 2015)

Exact and Approximate Algorithms for the Filter Design Optimization Problem. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Signal Process., 2015)

Quaternary Logic Lookup Table in Standard CMOS. - Diogo Brito; Taimur Gibran Rabuske; Jorge R. Fernandes; Paulo F. Flores; José Monteiro 001 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Multicore SIMD ASIP for Next-Generation Sequencing and Alignment Biochip Platforms. - Nuno Neves 002; Nuno Sebastião; David Martins de Matos; Pedro Tomás; Paulo F. Flores; Nuno Roma (IEEE Trans. Very Large Scale Integr. Syst., 2015)

A novel method for the approximation of multiplierless constant matrix vector multiplication. - Levent Aksoy; Paulo F. Flores; José Monteiro 001 (EURASIP J. Embed. Syst., 2016)

A variable RADIX-2r algorithm for single constant multiplication. - Ahmed Liacha; Abdelkrim Kamel Oudjida; Farid Ferguene; José Monteiro 001; Paulo F. Flores (NEWCAS, 2017)

Radix-2 r recoding with common subexpression elimination for multiple constant multiplication. - Ahmed Liacha; Abdelkrim Kamel Oudjida; Mohammed Bakiri; José Monteiro 001; Paulo F. Flores (IET Circuits Devices Syst., 2020)

AxASRE: A Novel Approach to Approximate Adder Synthesis Results Estimation. - Pedro Tauã Lopes Pereira; Guilherme Paim; Paulo F. Flores; Eduardo A. C. da Costa; Sergio Bampi (DSN-W, 2023)

EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (ETS, 2023)

Architectural Exploration for Energy-Efficient LMS and NLMS Adaptive Filters VLSI Design. - Pedro Tauã Lopes Pereira; Guilherme Paim; Eduardo A. C. da Costa; Paulo F. Flores; Sergio Bampi (NEWCAS, 2023)

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS. - Fabio Pavanello; Cédric Marchand 002; Ian O'Connor; Régis Orobtchouk; Fabien Mandorlo; Xavier Letartre; Sébastien Cueff; Elena-Ioana Vatajelu; Giorgio Di Natale; Benoit Cluzel; Aurelien Coillet; Benoît Charbonnier; et al. (CoRR, 2023)

Compact CMOS-Compatible Majority Gate Using Body Biasing in FDSOI Technology. - Brunno Alves de Abreu; Albi Mema; Simon Thomann; Guilherme Paim; Paulo F. Flores; Sergio Bampi; Hussam Amrouch (IEEE J. Emerg. Sel. Topics Circuits Syst., 2023)

MAxPy: A Framework for Bridging Approximate Computing Circuits to Its Applications. - Yuri Arbeletche; Guilherme Paim; Brunno Abreu; Sérgio Almeida 001; Eduardo Costa 001; Paulo F. Flores; Sergio Bampi (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

On the Efficacy and Vulnerabilities of Logic Locking in Tree-Based Machine Learning. - Brunno Alves de Abreu; Guilherme Paim; Lilas Alrahis; Paulo F. Flores; Ozgur Sinanoglu; Sergio Bampi; Hussam Amrouch (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)

ReAdapt-II: Energy-Quality Optimizations for VLSI Adaptive Filters Through Automatic Reconfiguration and Built-In Iterative Dividers. - Pedro Tauã Lopes Pereira; Patrícia Ücker Leleu da Costa; Eduardo A. C. da Costa; Paulo F. Flores; Sergio Bampi (IEEE Trans. Very Large Scale Integr. Syst., 2025)