CDFG -Petri Net Temporal Partitioning for Switching Context Applications. - Paulo Sérgio B. do Nascimento; Manoel Eusébio de Lima; Paulo Maciel 001 (SBCCI, 2002)

A partial reconfigurable architecture for controllers based on Petri nets. - Paulo Sérgio B. do Nascimento; Paulo Romero Martins Maciel; Manoel Eusébio de Lima; Remy Eskinazi Sant'Anna; Abel Guilhermino Silva-Filho (SBCCI, 2004)

A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only). - Paulo Sérgio B. do Nascimento; Paulo Romero Martins Maciel; Manoel Eusébio de Lima; Remy Eskinazi Sant'Anna; Abel Guilhermino Silva-Filho (FPGA, 2005)

A petri-net based Pre-runtime scheduler for dynamically self-reconfiguration of FPGAs (abstract only). - Remy Eskinazi Sant'Anna; Manoel Eusébio de Lima; Paulo Romero Martins Maciel; Carlos A. Valderrama; Abel Guilhermino Silva-Filho; Paulo Sérgio B. do Nascimento (FPGA, 2005)

An Energy-Aware Exploration Approach Based on Open Software Environment. - Abel G. Silva-Filho; Remy Eskinazi Sant'Anna; Paulo Sérgio Brandão do Nascimento; Manoel Eusébio de Lima (IESS, 2005)

A Timed Petri Net Approach for Pre-Runtime Scheduling in Partial and Dynamic Reconfigurable Systems. - Remy Eskinazi Sant'Anna; Manoel Eusébio de Lima; Paulo Romero Martins Maciel; Carlos A. Valderrama; Abel Guilhermino Silva-Filho; Paulo Sérgio B. do Nascimento (IPDPS, 2005)

Temporal partitioning for image processing based on time-space complexity in reconfigurable architectures. - Paulo Sérgio B. do Nascimento; Manoel Eusébio de Lima (DATE, 2006)

Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration. - Paulo Sérgio B. do Nascimento; Manoel Eusébio de Lima; Stelita M. da Silva; Jordana L. Seixas (SBCCI, 2006)

Aquarius: a dynamically reconfigurable computing platform. - Jordana L. Seixas; Edson Barbosa; Stelita M. da Silva; Paulo Sérgio B. do Nascimento; Vinícius Kursancew; Remy Eskinazi Sant'Anna; Edna Barros; Manoel Eusébio de Lima (SBCCI, 2007)

A Temporal Partitioning Methodology for Reconfigurable High Performance Computers. - Paulo Sérgio Brandão do Nascimento; Victor Wanderley Costa de Medeiros; Viviane Lucy Santos de Souza; Abner Corrêa Barros; Manoel Eusébio de Lima (ReConFig, 2008)

Implementation of a double-precision multiplier accumulator with exception treatment to a dense matrix multiplier module in FPGA. - Abner Corrêa Barros; Victor Wanderley Costa de Medeiros; Viviane Lucy Santos de Souza; Paulo Sérgio Brandão do Nascimento; Ângelo Mazer; João Paulo Fernandes Barbosa; Bruno P. Neves; Ismael Santos 001; Manoel Eusébio de Lima (SBCCI, 2008)

FPGA design methodology for DSP industrial applications - A case study of a three-phase positive-sequence detector. - Paulo Sérgio B. do Nascimento; Francisco A. S. Neves; Helber E. P. de Souza; Marco A. O. Domingues (SBCCI, 2012)

FPGA Implementation of the Generalized Delayed Signal Cancelation - Phase Locked Loop Method for Detecting Harmonic Sequence Components in Three-Phase Signals. - Paulo Sérgio B. do Nascimento; Helber E. P. de Souza; Francisco A. S. Neves; Leonardo R. Limongi (IEEE Trans. Ind. Electron., 2013)