Change-point detection method on 100 Gb/s ethernet interface. - Pavel Benácek; Rudolf B. Blazek; Tomás Cejka; Hana Kubátová (ANCS, 2014)

Architecture of Effective High-Speed Network Stream Merger. - Pavel Benácek; Hana Kubátová; Viktor Pus (DSD, 2014)

Application specific processor with high level synthesized instructions (abstract only). - Viktor Pus; Pavel Benácek (FPGA, 2014)

Trade-offs and progressive adoption of FPGA acceleration in network traffic monitoring. - Lukas Kekely; Viktor Pus; Pavel Benácek; Jan Korenek (FPL, 2014)

P4-to-VHDL: Automatic Generation of 100 Gbps Packet Parsers. - Pavel Benácek; Viktor Pus; Hana Kubátová (FCCM, 2016)

Line rate programmable packet processing in 100Gb networks. - Pavel Benácek; Viktor Pus; Jan Korenek; Michal Kekely (FPL, 2017)

Enhanced Flow Monitoring with P4 Generated Flexible Packet Parser. - Tomás Cejka; Petr Velan; Jirí Havránek; Pavel Benácek (AIMS, 2018)

Configurable FPGA Packet Parser for Terabit Networks with Guaranteed Wire-Speed Throughput. - Jakub Cabal; Pavel Benácek; Lukas Kekely; Michal Kekely; Viktor Pus; Jan Korenek (FPGA, 2018)

Verification of Generated RTL from P4 Source Code. - Radek Isa; Pavel Benácek; Viktor Pus (ICNP, 2018)

P4-To-VHDL: Automatic generation of high-speed input and output network blocks. - Pavel Benácek; Viktor Pus; Hana Kubátová; Tomás Cejka (Microprocess. Microsystems, 2018)

Accelerated DDoS Attacks Mitigation using Programmable Data Plane. - Mário Kuka; Kamil Vojanec; Jan Kucera 004; Pavel Benácek (ANCS, 2019)

Scalable P4 Deparser for Speeds Over 100 Gbps. - Jakub Cabal; Pavel Benácek; Jana Foltova; Juraj Holub (FCCM, 2019)