Dependability computations for fault-tolerant system based on FPGA. - Radek Dobias; Pavel Kubalík; Hana Kubátová (ICECS, 2005)

Dependability Computation for Fault Tolerant Reconfigurable Duplex System. - Pavel Kubalík; Radek Dobias; Hana Kubátová (DDECS, 2006)

Dependable Design for FPGA Based on Duplex System and Reconfiguration. - Pavel Kubalík; Radek Dobias; Hana Kubátová (DSD, 2006)

Fault Tolerant System Design Method Based on Self-Checking Circuits. - Pavel Kubalík; Petr Fiser; Hana Kubátová (IOLTS, 2006)

Fault Injection and Simulation for Fault Tolerant Reconfigurable Duplex System. - Pavel Kubalík; Jirí Kvasnicka; Hana Kubátová (DDECS, 2007)

An Efficient Multiple-Parity Generator Design for On-Line Testing on FPGA. - Petr Fiser; Pavel Kubalík; Hana Kubátová (DSD, 2008)

Experimental SEU Impact on Digital Design Implemented in FPGAs. - Jirí Kvasnicka; Pavel Kubalík; Hana Kubátová (DSD, 2008)

Dependable design technique for system-on-chip. - Pavel Kubalík; Hana Kubátová (J. Syst. Archit., 2008)

Reliable Railway Station System Based on Regular Structure Implemented in FPGA. - Jaroslav Borecký; Pavel Kubalík; Hana Kubátová (DSD, 2009)

Faults Coverage Improvement Based on Fault Simulation and Partial Duplication. - Jaroslav Borecký; Martin Kohlík; Hana Kubátová; Pavel Kubalík (DSD, 2010)

Fault Models Usability Study for On-line Tested FPGA. - Jaroslav Borecký; Martin Kohlík; Pavel Kubalík; Hana Kubátová (DSD, 2011)

Dedicated hardware implementation of a linear congruence solver in FPGA. - Jirí Bucek; Pavel Kubalík; Róbert Lórencz; Tomás Zahradnický (ICECS, 2012)

Comparison of FPGA and ASIC Implementation of a Linear Congruence Solver. - Jirí Bucek; Pavel Kubalík; Róbert Lórencz; Tomás Zahradnický (DSD, 2013)

An ASIC linear congruence solver synthesized with three cell libraries. - Jirí Bucek; Pavel Kubalík; Róbert Lórencz; Tomás Zahradnický (ICECS, 2014)

System on chip design of a linear system solver. - Jirí Bucek; Pavel Kubalík; Róbert Lórencz; Tomás Zahradnický (ISSoC, 2014)

LZ4 compression algorithm on FPGA. - Matej Bartik; Sven Ubik; Pavel Kubalík (ICECS, 2015)

A novel and efficient method to initialize FPGA embedded memory content in asymptotically constant time. - Matej Bartik; Sven Ubik; Pavel Kubalík (ReConFig, 2016)

Design of a Residue Number System Based Linear System Solver in Hardware. - Jirí Bucek; Pavel Kubalík; Róbert Lórencz; Tomás Zahradnický (J. Signal Process. Syst., 2017)

Performance Comparison of Multiple Approaches of Status Register for Medium Density Memory Suitable for Implementation of a Lossless Compression Dictionary: (Abstract Only). - Matej Bartík; Sven Ubik; Pavel Kubalík; Tomás Benes (FPGA, 2018)

Design of a High-Throughput Match Search Unit for Lossless Compression Algorithms. - Matej Bartik; Tomás Benes; Pavel Kubalík (CCWC, 2019)

Ultra High Resolution Jitter Measurement Method for Ethernet Based Networks. - Karel Hynek; Tomás Benes; Matej Bartik; Pavel Kubalík (CCWC, 2019)

High Throughput and Low Latency LZ4 Compressor on FPGA. - Tomás Benes; Matej Bartík; Pavel Kubalík (ReConFig, 2019)

Low Power Wireless Data Transfer for Internet of Things: GSM Network Measuring Results. - Vojtech Procházka; Pavel Kubalík; Hana Kubátová (MECO, 2020)

An In-Sight Into How Compression Dictionary Architecture Can Affect the Overall Performance in FPGAs. - Matej Bartík; Tomás Benes; Pavel Kubalík (IEEE Access, 2020)

Feasibility of a Neural Network with Linearly Approximated Functions on Zynq FPGA. - Miroslav Skrbek; Pavel Kubalík (ICECS 2022, 2022)

Approximate arithmetic for modern neural networks and FPGAs. - Miroslav Skrbek; Pavel Kubalík (MECO, 2022)

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA. - Miroslav Skrbek; Pavel Kubalík; Martin Kohlík; Jaroslav Borecký; Robert Hülle (MECO, 2023)

Quantized Neural Network with Linearly Approximated Functions on Zynq FPGA. - Miroslav Skrbek; Pavel Kubalík; Martin Kohlík; Jaroslav Borecký; Robert Hülle (MECO, 2024)