Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed. - Evangelia Kassapaki; Pavlos M. Mattheakis; Christos P. Sotiriou (FPL, 2006)

A polynomial time flow for implementing free-choice Petri-nets. - Pavlos M. Mattheakis; Christos P. Sotiriou; Peter A. Beerel (ICCD, 2012)

Polynomial Complexity Asynchronous Control Circuit Synthesis of Concurrent Specifications Based on Burst-Mode FSM Decomposition. - Pavlos M. Mattheakis; Christos P. Sotiriou (VLSI Design, 2013)

Significantly reducing MPI intercommunication latency and power overhead in both embedded and HPC systems. - Pavlos M. Mattheakis; Ioannis Papaefstathiou (ACM Trans. Archit. Code Optim., 2013)

Logic synthesis of concurrent control specifications - Pavlos M. Mattheakis (2013)

Hardware primitives for the synthesis of multithreaded elastic systems. - Giorgos Dimitrakopoulos; I. Seitanidis; Anastasios Psarras; K. Tsiouris; Pavlos M. Mattheakis; Jordi Cortadella (DATE, 2014)

Skew Bounded Buffer Tree Resynthesis For Clock Power Optimization. - Subhendu Roy; David Z. Pan; Pavlos M. Mattheakis; Peter S. Colyer; Laurent Masse-Navette; Pierre-Olivier Ribet (ACM Great Lakes Symposium on VLSI, 2015)

Clock Tree Resynthesis for Multi-Corner Multi-Mode Timing Closure. - Subhendu Roy; Pavlos M. Mattheakis; Laurent Masse-Navette; David Z. Pan (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

A Low-Power Network-on-Chip Architecture for Tile-based Chip Multi-Processors. - Anastasios Psarras; Junghee Lee; Pavlos M. Mattheakis; Chrysostomos Nicopoulos; Giorgos Dimitrakopoulos (ACM Great Lakes Symposium on VLSI, 2016)

Accelerating Intercommunication in Highly Parallel Systems. - Nikolaos Tampouratzis; Pavlos M. Mattheakis; Ioannis Papaefstathiou (ACM Trans. Archit. Code Optim., 2016)

Timing Driven Incremental Multi-Bit Register Composition Using a Placement-Aware ILP formulation. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (DAC, 2017)

Timing-Driven and Placement-Aware Multibit Register Composition. - Ioannis Seitanidis; Giorgos Dimitrakopoulos; Pavlos M. Mattheakis; Laurent Masse-Navette; David G. Chinnery (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Soft-Clustering Driven Flip-flop Placement Targeting Clock-induced OCV. - Dimitrios Mangiras; Pavlos M. Mattheakis; Pierre-Olivier Ribet; Giorgos Dimitrakopoulos (ISPD, 2020)