Static Noise Margin based Yield Modelling of 6T SRAM for Area and Minimum Operating Voltage Improvement using Recovery Techniques. - Nidhi Batra; Pawan Sehgal; Shashwat Kaushik; Mohammad S. Hashmi; Sudesh Bhalla; Anuj Grover (ACM Great Lakes Symposium on VLSI, 2016)

An Efficient Approach Targeting Broken Topological Clock Path for Master - Generated Clock Pair. - Pawan Sehgal; Akhilesh C. Mishra; Rangarajan Ramanujam; Sujay Deb (iNIS, 2016)

An effective and efficient algorithm to analyse and debug clock propagation issues. - Pawan Sehgal; Aditi Sharma; Akhilesh C. Mishra; Rangarajan Ramanujam; Sujay Deb (VDAT, 2016)

A 14-bit 6.7 MS/s 0.018 mm2 98 μW SAR A/D Converter With On-the-Fly Autocalibration for Array Applications. - Sanjoy Kumar Dey; Arun Kumar Barman; Pawan Sehgal; Mukul Sarkar; Shouribrata Chatterjee (IEEE Trans. Very Large Scale Integr. Syst., 2025)