Comparison of the Hardware Performance of the AES Candidates Using Reconfigurable Hardware. - Kris Gaj; Pawel Chodowiec (AES Candidate Conference, 2000)

Fast Implementation and Fair Comparison of the Final Candidates for Advanced Encryption Standard Using Field Programmable Gate Arrays. - Kris Gaj; Pawel Chodowiec (CT-RSA, 2001)

Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining. - Pawel Chodowiec; Po Khuon; Kris Gaj (FPGA, 2001)

Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. - Pawel Chodowiec; Kris Gaj; Peter Bellows; Brian Schott (ISC, 2001)

Very Compact FPGA Implementation of the AES Algorithm. - Pawel Chodowiec; Kris Gaj (CHES, 2003)

IPsec-Protected Transport of HDTV over IP. - Peter Bellows; Jaroslav Flidr; Ladan Gharai; Colin Perkins; Pawel Chodowiec; Kris Gaj (FPL, 2003)

InvMixColumn decomposition and multilevel resource sharing in AES implementations. - Viktor Fischer; Milos Drutarovský; Pawel Chodowiec; F. Gramain (IEEE Trans. Very Large Scale Integr. Syst., 2005)

FPGA and ASIC Implementations of AES. - Kris Gaj; Pawel Chodowiec (Cryptographic Engineering, 2009)