Design Considerations for Reconfigurable Delay Circuit to Emulate System Critical Paths. - Xiaobin Yuan; Pawel Owczarczyk; Alan J. Drake; Marshall D. Tiner; David T. Hui; John P. Pennings; Francesco A. Campisano; Richard L. Willaman; Leana M. Cropp; Rudolph D. Dussault (IEEE Trans. Very Large Scale Integr. Syst., 2015)

26.5 Adaptive clocking in the POWER9™ processor for voltage droop protection. - Michael S. Floyd; Phillip J. Restle; Michael A. Sperling; Pawel Owczarczyk; Eric J. Fluhr; Joshua Friedrich; Paul Muench; Timothy Diemoz; Pierce Chuang; Christos Vezyrtzis (ISSCC, 2017)

Droop mitigation using critical-path sensors and an on-chip distributed power supply estimation engine in the z14™ enterprise processor. - Christos Vezyrtzis; Thomas Strach; Pierce I-Jen Chuang; Preetham Lobo; Richard F. Rizzolo; Tobias Webel; Pawel Owczarczyk; Alper Buyuktosunoglu; Ramon Bertran; David T. Hui; Susan M. Eickhoff; Michael S. Floyd; et al. (ISSCC, 2018)

The 24-Core POWER9 Processor With Adaptive Clocking, 25-Gb/s Accelerator Links, and 16-Gb/s PCIe Gen4. - Christopher J. Gonzalez; Michael S. Floyd; Eric Fluhr; Phillip J. Restle; Daniel Dreps; Michael A. Sperling; Rahul M. Rao; David Hogenmiller; Christos Vezyrtzis; Pierce Chuang; Daniel Lewis; Ricardo Escobar; et al. (IEEE J. Solid State Circuits, 2018)

IBM z14: Processor Characterization and Power Management for High-Reliability Mainframe Systems. - Christopher J. Berry; David Wolpert 001; Christos Vezyrtzis; Richard F. Rizzolo; Sean M. Carey; Yaniv Maroz; Hunter F. Shi; Dureseti Chidambarrao; Christian Jacobi 002; Anthony Saporito; Thomas Strach; Alper Buyuktosunoglu; et al. (IEEE J. Solid State Circuits, 2019)