FPGA implementation of 3-D separable Gauss filter using pipeline rotation structures. - Krzysztof Wawryn; Pawel Poczekajlo; Robert T. Wirski (MIXDES, 2015)

Hardware implementation of 3D pipelined laplace filter based on rotation structures. - Pawel Poczekajlo; Krzysztof Wawryn (MIXDES, 2017)

Synthesis and Realization of 3-D Orthogonal FIR Filters Using Pipeline Structures. - Pawel Poczekajlo; Robert T. Wirski (Circuits Syst. Signal Process., 2018)

Algorithm for realisation, parameter analysis, and measurement of pipelined separable 3D finite impulse response filters composed of Givens rotation structures. - Pawel Poczekajlo; Krzysztof Wawryn (IET Signal Process., 2018)

Modern computing methods for digital signal processing engineering systems. - Pawel Poczekajlo; Robert Suszynski (KES, 2021)

The latest developments in computer science and their impact on space exploration. - Robert Suszynski; Pawel Poczekajlo (KES, 2021)

Synthesis algorithm of low sensitivity non-separable N-D finite impulse response filters configured of fast orthogonal 1-D rotation structures implemented in field programmable gate arrays IC. - Pawel Poczekajlo; Krzysztof Wawryn (IET Signal Process., 2022)

An attempt at the possibility of using multi-output paraunitary filters for image processing for astrophotography trackers. - Pawel Poczekajlo; Robert Suszynski (KES, 2023)

The use of modern methods of virtualization and shared network functions to optimize the resources used. - Pawel Poczekajlo; Robert Suszynski; Andrzej Antosz (KES, 2023)

2-D lossless FIR filter design using synthesis of the paraunitary transfer function matrix. - Krzysztof Wawryn; Pawel Poczekajlo (Int. J. Appl. Math. Comput. Sci., 2023)

Modified CORDIC Algorithm for Givens Rotator. - Pawel Poczekajlo; Leonid V. Moroz; Ewa Deelman; Pawel Gepner (ICCS (6), 2024)

Implementation of a universal replicable DSP core in FPGA devices for cascade audio signal processing applications. - Lukasz Golka; Pawel Poczekajlo; Robert Suszynski (KES, 2024)

Iterative computing algorithms implemented in FPGA using ALTERA_CORDIC library as an example. - Pawel Poczekajlo (KES, 2024)

The concept of multicore computing and processing in a field-programmable gate array chip. - Pawel Poczekajlo; Lukasz Golka; Robert Suszynski; Patryk Widulinski (KES, 2024)

Engineering energy measurement system and data analising for an electric elevator. - Pawel Poczekajlo; Robert Suszynski; Andrzej Antosz (KES, 2024)

Low Latency Recoding CORDIC Algorithm for FPGA Implementation. - Pawel Poczekajlo; Leonid V. Moroz; Ewa Deelman; Michela Taufer; Pawel Gepner; Jerzy Krawiec (ICCS (3), 2025)

Evaluation of new CORDIC algorithms implemented on FPGA for the Givens Rotator. - Pawel Poczekajlo; Leonid V. Moroz; Ewa Deelman; Pawel Gepner (J. Comput. Sci., 2025)