The VPI-Based Combinational IP Core Module-Based Mixed Level Serial Fault Simulation and Test Generation Methodology. - Pedram A. Riahi; Zainalabedin Navabi; Fabrizio Lombardi (Asian Test Symposium, 2003)

Using Verilog VPI for Mixed Level Serial Fault Simulation in a Test Generation Environment. - Pedram A. Riahi; Zainalabedin Navabi; Fabrizio Lombardi (Embedded Systems and Applications, 2003)

Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture. - Shervin Sharifi; Mohammad Hosseinabady; Pedram A. Riahi; Zainalabedin Navabi (DFT, 2003)

Simulating Faults of Combinational IP Core-based SOCs in a PLI Environment. - Pedram A. Riahi; Zainalabedin Navabi; Fabrizio Lombardi (DFT, 2005)

A Flow Graph Technique for DFT Controller Modification. - Mohammad Hosseinabady; Pejman Lotfi-Kamran; Pedram A. Riahi; Fabrizio Lombardi; Zainalabedin Navabi (SoCC, 2005)