A confidence assessment of WCET estimates for software time randomized caches. - Pedro Benedicte; Leonidas Kosmidis; Eduardo Quiñones; Jaume Abella 001; Francisco J. Cazorla (INDIN, 2016)

Modelling the confidence of timing analysis for time randomised caches. - Pedro Benedicte; Leonidas Kosmidis; Eduardo Quiñones; Jaume Abella 001; Francisco J. Cazorla (SIES, 2016)

Design and integration of hierarchical-placement multi-level caches for real-time systems. - Pedro Benedicte; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (DATE, 2018)

HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems. - Pedro Benedicte; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (ECRTS, 2018)

RPR: a random replacement policy with limited pathological replacements. - Pedro Benedicte; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (SAC, 2018)

Towards limiting the impact of timing anomalies in complex real-time processors. - Pedro Benedicte; Jaume Abella 001; Carles Hernández 001; Enrico Mezzetti; Francisco J. Cazorla (ASP-DAC, 2019)

LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache. - Pedro Benedicte; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (DATE, 2019)

Performance Analysis and Optimization of Automotive GPUs. - Fabio Mazzocchetti; Pedro Benedicte; Hamid Tabani; Leonidas Kosmidis; Jaume Abella 001; Francisco J. Cazorla (SBAC-PAD, 2019)

Locality-aware cache random replacement policies. - Pedro Benedicte; Carles Hernández 001; Jaume Abella 001; Francisco J. Cazorla (J. Syst. Archit., 2019)

Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP). - Jeremy Giesen; Pedro Benedicte; Enrico Mezzetti; Jaume Abella 001; Francisco J. Cazorla (RTAS, 2020)

SafeTI: a Hardware Traffic Injector for MPSoC Functional and Timing Validation. - Oriol Sala; Sergi Alcaide; Guillem Cabo; Francisco Bas; Ruben Lorenzo; Pedro Benedicte; David Trilla; Guillermo Gil; Fabio Mazzocchetti; Jaume Abella 001 (IOLTS, 2021)

Performance Analysis and Optimization Opportunities for NVIDIA Automotive GPUs. - Hamid Tabani; Fabio Mazzocchetti; Pedro Benedicte; Jaume Abella 001; Francisco J. Cazorla (J. Parallel Distributed Comput., 2021)

SafeDM: a Hardware Diversity Monitor for Redundant Execution on Non-Lockstepped Cores. - Francisco Bas; Pedro Benedicte; Sergi Alcaide; Guillem Cabo; Fabio Mazzocchetti; Jaume Abella 001 (DATE, 2022)

SafeSU-2: a Safe Statistics Unit for Space MPSoCs. - Guillem Cabo; Sergi Alcaide; Carles Hernández 001; Pedro Benedicte; Francisco Bas; Fabio Mazzocchetti; Jaume Abella 001 (DATE, 2022)

De-RISC: A Complete RISC-V Based Space-Grade Platform. - Nils-Johan Wessman; Fabio Malatesta; Stefano Ribes; Jan Andersson; Antonio García-Vilanova; Miguel Masmano; Vicente Nicolau; Paco Gomez; Jimmy Le Rhun; Sergi Alcaide; Guillem Cabo; Francisco Bas; et al. (DATE, 2022)

SafeX: Open Source Hardware and Software Components for Safety-Critical Systems. - Sergi Alcaide; Guillem Cabo; Francisco Bas; Pedro Benedicte; Francisco Fuentes; Feng Chang; Ilham Lasfar; Ramon Canal; Jaume Abella 001 (FDL, 2022)

SafeDX: Standalone Modules Providing Diverse Redundancy for Safety-Critical Applications. - Ramon Canal; Francisco Bas; Sergi Alcaide; Guillem Cabo; Pedro Benedicte; Francisco Fuentes; Feng Chang; Ilham Lasfar; Jaume Abella 001 (SAMOS, 2022)

SafeSoftDR: A Library to Enable Software-based Diverse Redundancy for Safety-Critical Tasks. - Fabio Mazzocchetti; Sergi Alcaide; Francisco Bas; Pedro Benedicte; Guillem Cabo; Feng Chang; Francisco Fuentes; Jaume Abella 001 (CoRR, 2022)

End-to-End QoS for the Open Source Safety-Relevant RISC-V SELENE Platform. - Pablo Andreu; Carles Hernández 001; Tomás Picornell; Pedro López 001; Sergi Alcaide; Francisco Bas; Pedro Benedicte; Guillem Cabo; Feng Chang; Francisco Fuentes; Jaume Abella 001 (CoRR, 2022)

Smart hardware designs for probabilistically-analyzable processor architectures. - Pedro Benedicte Illescas (2022)

SafeSU-2L: An Advanced Multicore Interference Statistics Unit for a RISC-V Space SoC. - Francisco Bas; Sergi Alcaide; Guillem Cabo; Ilham Lasfar; Feng Chang; Francisco Fuentes; Ramon Canal; Pedro Benedicte; Juan Carlos Rodriguez; Jaume Abella 001 (IEEE Trans. Aerosp. Electron. Syst., 2025)