Leakage Energy Reduction in Banked Content Addressable Memories. - Pedro Echeverría; José Luis Ayala; Marisa López-Vallejo (ICECS, 2006)

An FPGA run-time parameterisable Log-Normal Random Number Generator. - Pedro Echeverría; David B. Thomas; Marisa López-Vallejo; Wayne Luk (ARC, 2008)

Designing Highly Parameterized Hardware using xHdl. - Miguel Angel Sánchez; Pedro Echeverría; Francisco Mansilla; Marisa López-Vallejo (FDL, 2008)

Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach. - Pedro Echeverría; Marisa López-Vallejo; Jose María Pesquero (ICECS, 2008)

Experimental methodology for power characterization of FPGAs. - Ignacio Herrera-Alzu; Miguel Angel Sánchez; Marisa López-Vallejo; Pedro Echeverría (ICECS, 2008)

Power Considerations in Banked CAMs: A Leakage Reduction Approach. - Pedro Echeverría Aramendi; José L. Ayala; Marisa López-Vallejo (VLSI Design, 2008)

Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs. - Pedro Echeverría; Marisa López-Vallejo; Walter Bolognesi; Carlos A. López-Barrio (ICECS, 2009)

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs. - Pedro Echeverría; Marisa López-Vallejo (Microprocess. Microsystems, 2011)

Floating-Point Exponentiation Units for Reconfigurable Computing. - Florent de Dinechin; Pedro Echeverría; Marisa López-Vallejo; Bogdan Pasca 001 (ACM Trans. Reconfigurable Technol. Syst., 2013)

High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator. - Pedro Echeverría; Marisa López-Vallejo (J. Signal Process. Syst., 2013)