Adding Instruction Cache Effect to an Exact Schedulability Analysis of Preemptive Real-Time Systems. - José V. Busquets-Mataix; Juan José Serrano; Rafael Ors Carot; Pedro J. Gil; Andrew J. Wellings (RTS, 1996)

Dependability Models of RAID Using Stochastic Activity Networks. - Vicente Santonja; Marina Alonso; Xavier Molero; Juan José Serrano; Pedro J. Gil; Rafael Ors (EDCC, 1996)

Adding instruction cache effect to schedulability analysis of preemptive real-time systems. - José V. Busquets-Mataix; Juan José Serrano; Rafael Ors; Pedro J. Gil; Andy J. Wellings (IEEE Real Time Technology and Applications Symposium, 1996)

Using harmonic task-sets to increase the schedulable utilization of cache-based preemptive real-time systems. - José V. Busquets-Mataix; Juan José Serrano; Rafael Ors; Pedro J. Gil; Andy J. Wellings (RTCSA, 1996)

Fault Injection into VHDL Models: Analysis of the Error Syndrome of a Microcomputer System. - Daniel Gil; Juan Carlos Baraza; J. V. Busquets; Pedro J. Gil (EUROMICRO, 1998)

Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System. - Daniel Gil; R. Martínez; J. V. Busquets; Juan Carlos Baraza; Pedro J. Gil (EDCC, 1999)

Dependability Evaluation of Fault Tolerant Distributed Industrial Control Systems. - José Carlos Campelo; Pedro Yuste; Francisco Rodríguez 003; Pedro J. Gil; Juan José Serrano (IPPS/SPDP Workshops, 1999)

Hierarchical Reliability and Safety Models of Fault Tolerant Distributed Industrial Control Systems. - José Carlos Campelo; Pedro Yuste; Francisco Rodríguez 003; Pedro J. Gil; Juan José Serrano (SAFECOMP, 1999)

Design and Validation of a Distributed Industrial Control System's Nodes. - José Carlos Campelo; Francisco Rodríguez 003; Pedro J. Gil; Juan José Serrano (SRDS, 1999)

Distributed industrial control systems: a fault-tolerant architecture. - José Carlos Campelo; Francisco Rodríguez 003; Alicia Rubio; Rafael Ors; Pedro J. Gil; Lenin Lemus; J. V. Busquets; José Albaladejo; Juan José Serrano (Microprocess. Microsystems, 1999)

A Prototype of a VHDL-Based Fault Injection Tool. - Juan Carlos Baraza; Joaquin Gracia; Daniel Gil; Pedro J. Gil (DFT, 2000)

An alternative to unify performance and reliability analysis of industrial applications. - Lenin Lemus; David de Andrés; Pedro J. Gil (ESM, 2000)

A Study of the Effects of Transient Fault Injection into the VHDL Model of a Fault-Tolerant Microcomputer System. - Daniel Gil; Joaquin Gracia; Juan Carlos Baraza; Pedro J. Gil (IOLTW, 2000)

Techniques to increase the schedulable utilization of cache-based preemptive real-time systems. - José V. Busquets-Mataix; Daniel Gil; Pedro J. Gil; Andy J. Wellings (J. Syst. Archit., 2000)

Comparison and Application of Different VHDL-Based Fault Injection Techniques. - Joaquin Gracia; Juan Carlos Baraza; Daniel Gil; Pedro J. Gil (DFT, 2001)

A Study of the Experimental Validation of Fault-Tolerant Systems Using Different VHDL-Based Fault Injection Techniques. - Joaquin Gracia; Juan Carlos Baraza; Daniel Gil; Pedro J. Gil (IOLTW, 2001)

A Fault Hypothesis Study on the TTP/C Using VHDL-Based and Pin-Level Fault Injection Techniques. - Sara Blanc; Joaquin Gracia; Pedro J. Gil (DFT, 2002)

Using VHDL-Based Fault Injection to exercise Error Detection Mechanisms in the Time-Triggered Architecture. - Joaquin Gracia; Daniel Gil; Juan Carlos Baraza; Pedro J. Gil (PRDC, 2002)

A prototype of a VHDL-based fault injection tool: description and application. - Juan Carlos Baraza; Joaquin Gracia; Daniel Gil; Pedro J. Gil (J. Syst. Archit., 2002)

INERTE: Integrated NExus-Based Real-Time Fault Injection Tool for Embedded Systems. - Pedro Yuste; David de Andrés; Lenin Lemus; Juan José Serrano; Pedro J. Gil (DSN, 2003)

Non-intrusive Software-Implemented Fault Injection in Embedded Systems. - Pedro Yuste; Juan-Carlos Ruiz-Garcia 001; Lenin Lemus; Pedro J. Gil (LADC, 2003)

Improving the Multiple Errors Detection Coverage in Distributed Embedded Systems. - Sara Blanc; Pedro J. Gil (SRDS, 2003)

Study, comparison and application of different VHDL-based fault injection techniques for the experimental validation of a fault-tolerant system. - Daniel Gil; Joaquin Gracia; Juan Carlos Baraza; Pedro J. Gil (Microelectron. J., 2003)

Experiences during the Experimental Validation of the Time-Triggered Architecture. - Sara Blanc; Joaquin Gracia; Pedro J. Gil (DATE, 2004)

On Benchmarking the Dependability of Automotive Engine Control Applications. - Juan-Carlos Ruiz-Garcia 001; Pedro Yuste; Pedro J. Gil; Lenin Lemus (DSN, 2004)

Analysis of the influence of processor hidden registers on the accuracy of fault injection techniques. - Daniel Gil; Joaquin Gracia; Juan Carlos Baraza; Pedro J. Gil (HLDVT, 2004)

Fast Run-Time Reconfiguration for SEU Injection. - David de Andrés; José Albaladejo; Lenin Lemus; Pedro J. Gil (EDCC, 2005)

Impact of Faults in Combinational Logic of Commercial Microcontrollers. - Daniel Gil; Joaquin Gracia; Juan Carlos Baraza; Pedro J. Gil (EDCC, 2005)

Improvement of fault injection techniques based on VHDL code modification. - Juan Carlos Baraza; Joaquin Gracia; Daniel Gil; Pedro J. Gil (HLDVT, 2005)

On-chip Debugging-based Fault Emulation for Robustness Evaluation of Embedded Software Components. - Juan-Carlos Ruiz-Garcia 001; José Carlos Campelo; Pedro J. Gil; Juan Pardo (PRDC, 2005)

Run-Time Reconfiguration for Emulating Transient Faults in VLSI Systems. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (DSN, 2006)

Temporal Characterization of Embedded Systems Using Nexus. - Juan Pardo; José Carlos Campelo; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (EDCC, 2006)

Fast Emulation of Permanent Faults in VLSI Systems. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (FPL, 2006)

FADES: a fault emulation tool for fast dependability assessment. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (FPT, 2006)

Analysis of the influence of intermittent faults in a microcontroller. - Joaquin Gracia; Luis J. Saiz; Juan Carlos Baraza; Daniel Gil; Pedro J. Gil (DDECS, 2008)

Dependability Assessment for the Selection of Embedded Cores. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (EDCC, 2008)

Injecting intermittent faults for the dependability validation of commercial microcontrollers. - Daniel Gil; Luis J. Saiz; Joaquin Gracia; Juan Carlos Baraza; Pedro J. Gil (HLDVT, 2008)

Generic Design and Automatic Deployment of NMR Strategies on HW Cores. - Juan-Carlos Ruiz-Garcia 001; David de Andrés; Sara Blanc; Pedro J. Gil (PRDC, 2008)

Fault Emulation for Dependability Evaluation of VLSI Systems. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Daniel Gil; Pedro J. Gil (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Enhancement of Fault Injection Techniques Based on the Modification of VHDL Code. - Juan Carlos Baraza; Joaquin Gracia; Sara Blanc; Daniel Gil; Pedro J. Gil (IEEE Trans. Very Large Scale Integr. Syst., 2008)

Design and Deployment of a Generic ECC-based Fault Tolerance Mechanism for Embedded HW Cores. - Juan-Carlos Ruiz-Garcia 001; David de Andrés; Pedro J. Gil (ETFA, 2009)

Using Dependability, Performance, Area and Energy Consumption Experimental Measures to Benchmark IP Cores. - David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (LADC, 2009)

An Attack Injection Approach to Evaluate the Robustness of Ad Hoc Networks. - David de Andrés; Jesus Friginal; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (PRDC, 2009)

Dependability assessment of by-wire control systems using fault injection. - Sara Blanc; Alberto Bonastre; Pedro J. Gil (J. Syst. Archit., 2009)

Experimental validation of a fault tolerant microcomputer system against intermittent faults. - Joaquin Gracia-Moran; Daniel Gil-Tomas; Luis J. Saiz-Adalid; Juan Carlos Baraza; Pedro J. Gil-Vicente (DSN, 2010)

Searching Representative and Low Cost Fault Models for Intermittent Faults in Microcontrollers: A Case Study. - Joaquin Gracia-Moran; Daniel Gil-Tomas; Juan Carlos Baraza; Luis J. Saiz-Adalid; Pedro J. Gil-Vicente (PRDC, 2010)

Attack Injection to Support the Evaluation of Ad Hoc Networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (SRDS, 2010)

Coarse-grained resilience benchmarking using logic score of preferences: ad hoc networks as a case study. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (EWDC, 2011)

On Selecting Representative Faultloads to Guide the Evaluation of Ad Hoc Networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (LADC, 2011)

Using Performance, Energy Consumption, and Resilience Experimental Measures to Evaluate Routing Protocols for Ad Hoc Networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (NCA, 2011)

Resilience-Driven Parameterisation of Ad Hoc Routing Protocols: olsrd as a Case Study. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (SRDS, 2011)

Towards benchmarking routing protocols in wireless mesh networks. - Jesus Friginal; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (Ad Hoc Networks, 2011)

Tolerating multiple faults with proximate manifestations in FPGA-based critical designs for harsh environments. - Jaime Espinosa; David de Andrés; Juan Carlos Ruiz 001; Pedro J. Gil (FPL, 2012)

Analyzing the Impact of Intermittent Faults on Microprocessors Applying Fault Injection. - Daniel Gil-Tomas; Joaquin Gracia-Moran; Juan-Carlos Baraza-Calvo; Luis J. Saiz-Adalid; Pedro J. Gil-Vicente (IEEE Des. Test, 2012)

Studying the effects of intermittent faults on a microcontroller. - Daniel Gil-Tomas; Joaquin Gracia-Moran; Juan-Carlos Baraza-Calvo; Luis J. Saiz-Adalid; Pedro J. Gil-Vicente (Microelectron. Reliab., 2012)

The Challenge of Detection and Diagnosis of Fugacious Hardware Faults in VLSI Designs. - Jaime Espinosa; David de Andrés; Juan-Carlos Ruiz-Garcia 001; Pedro J. Gil (EWDC, 2013)

Improving the Transfer of Safety and Security Competences to Industry: The RISKY Approach. - Joaquin Gracia-Moran; Juan-Carlos Ruiz-Garcia 001; Juan-Carlos Baraza-Calvo; David de Andrés; Pedro J. Gil (EWDC, 2013)

Using Interleaving to Avoid the Effects of Multiple Adjacent Faults in On-Chip Interconnection Lines. - Luis J. Saiz-Adalid; Pedro J. Gil; Joaquin Gracia-Moran; Juan-Carlos Baraza-Calvo (EWDC, 2013)

Defining a Representative and Low Cost Fault Model Set for Intermittent Faults in Microprocessor Buses. - Joaquin Gracia-Moran; Daniel Gil-Tomas; Luis J. Saiz-Adalid; Juan-Carlos Baraza-Calvo; Pedro J. Gil-Vicente (LADC, 2013)

Flexible Unequal Error Control Codes with Selectable Error Detection and Correction Levels. - Luis J. Saiz-Adalid; Pedro J. Gil-Vicente; Juan-Carlos Ruiz-Garcia 001; Daniel Gil-Tomas; Juan Carlos Baraza; Joaquin Gracia-Moran (SAFECOMP, 2013)

Modified Hamming Codes to Enhance Short Burst Error Detection in Semiconductor Memories (Short Paper). - Luis J. Saiz-Adalid; Pedro J. Gil; Juan-Carlos Baraza-Calvo; Juan-Carlos Ruiz-Garcia 001; Daniel Gil-Tomas; Joaquin Gracia-Moran (EDCC, 2014)

Effects of Intermittent Faults on the Reliability of a Reduced Instruction Set Computing (RISC) Microprocessor. - Joaquin Gracia-Moran; Juan-Carlos Baraza-Calvo; Daniel Gil-Tomas; Luis J. Saiz-Adalid; Pedro J. Gil-Vicente (IEEE Trans. Reliab., 2014)

Increasing the Dependability of VLSI Systems through Early Detection of Fugacious Faults. - Jaime Espinosa; David de Andrés; Pedro J. Gil (EDCC, 2015)

Ultrafast Single Error Correction Codes for Protecting Processor Registers. - Luis J. Saiz-Adalid; Pedro J. Gil; Joaquin Gracia-Moran; Daniel Gil-Tomas; Juan-Carlos Baraza-Calvo (EDCC, 2015)

MCU Tolerance in SRAMs Through Low-Redundancy Triple Adjacent Error Correction. - Luis J. Saiz-Adalid; Pedro Reviriego; Pedro J. Gil; Salvatore Pontarelli; Juan Antonio Maestro (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Ultrafast Error Correction Codes for Double Error Detection/Correction. - Luis J. Saiz-Adalid; Pedro J. Gil; Juan Carlos Ruiz 001; Joaquin Gracia-Moran; Daniel Gil-Tomas; Juan-Carlos Baraza-Calvo (EDCC, 2016)

Speeding-Up Simulation-Based Fault Injection of Complex HDL Models. - Ilya Tuzov; Juan Carlos Ruiz 001; David de Andrés; Pedro J. Gil (LADC, 2016)

Injecting Intermittent Faults for the Dependability Assessment of a Fault-Tolerant Microcomputer System. - Daniel Gil-Tomas; Joaquin Gracia-Moran; Juan-Carlos Baraza-Calvo; Luis J. Saiz-Adalid; Pedro J. Gil-Vicente (IEEE Trans. Reliab., 2016)

Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes. - Joaquin Gracia-Moran; Luis J. Saiz-Adalid; Juan-Carlos Baraza-Calvo; Pedro J. Gil (LADC, 2018)

Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications. - Joaquin Gracia-Moran; Luis J. Saiz-Adalid; Daniel Gil-Tomas; Pedro J. Gil-Vicente (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection. - Luis J. Saiz-Adalid; Joaquin Gracia-Moran; Daniel Gil-Tomas; Juan-Carlos Baraza-Calvo; Pedro J. Gil-Vicente (IEEE Access, 2019)

A Hybrid Technique Based on ECC and Hardened Cells for Tolerating Random Multiple-Bit Upsets in SRAM Arrays. - Daniel Gil-Tomas; Luis J. Saiz-Adalid; Joaquin Gracia-Moran; Juan-Carlos Baraza-Calvo; Pedro J. Gil-Vicente (IEEE Access, 2024)