An FPGA-Based Architecture for the Versatile Video Coding Multiple Transform Selection Core. - Matías J. Garrido; Fernando Pescador; Miguel Chavarrías; Pedro J. Lobo; César Sanz; Pedro Paz (IEEE Access, 2020)

Optimum MDC FFT Hardware Architectures in Terms of Delays and Multiplexers. - Mario Garrido; Pedro Paz (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 5.2-GS/s 8-Parallel 1024-Point MDC FFT. - Pedro Paz; Mario Garrido (DCIS, 2023)

Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices. - Pedro Paz; Mario Garrido (J. Signal Process. Syst., 2023)

CORDIC-Based Computation of Arcsine and Arccosine Functions on FPGA. - Pedro Paz; Mario Garrido (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

A 12.8-GS/s 32-Parallel 1 Million-Point FFT. - Pedro Paz; Mario Garrido (DCIS, 2024)