Utilizing High-Level Information for Formal Hardware Verification. - Peer Johannsen; Rolf Drechsler (ACS, 2001)

BooStER: Speeding Up RTL Property Checking of Digital Designs by Word-Level Abstarction. - Peer Johannsen (CAV, 2001)

Reducing bitvector satisfiability problems to scale down design sizes for RTL property checking. - Peer Johannsen (HLDVT, 2001)

Speeding Up Verification of RTL Designs by Computing One-to-one Abstractions with Reduced Signal Widths. - Peer Johannsen; Rolf Drechsler (VLSI-SOC, 2001)

Speeding up hardware verification by automated data path scaling. - Peer Johannsen (2002)