Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors. - Pegdwende Romaric Nikiema; Angeliki Kritikakou; Marcello Traiola; Olivier Sentieys (DSN-S, 2023)

Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead. - Pegdwende Romaric Nikiema; Angeliki Kritikakou; Marcello Traiola; Olivier Sentieys (ECRTS, 2023)

Towards Dependable RISC-V Cores for Edge Computing Devices. - Pegdwende Romaric Nikiema; Alessandro Palumbo; Allan Aasma; Luca Cassano; Angeliki Kritikakou; Ari Kulmala; Jari Lukkarila; Marco Ottavi; Rafail Psiakis; Marcello Traiola (IOLTS, 2023)

Special Session: Impact of Compiler Optimizations on the Reliability of a RISC-V-Based Core. - Pegdwende Romaric Nikiema; Marcello Traiola; Angeliki Kritikakou (DFT, 2024)