Pei Liu
Orcid: 0000-0001-7769-7123Affiliations:
- KTH Royal Institute of Technology, School of ICT, Department of Electronic Systems, Stockholm, Sweden
According to our database1,
Pei Liu
authored at least 8 papers
between 2010 and 2017.
Collaborative distances:
Collaborative distances:
Timeline
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Bibliography
2017
A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture.
J. Signal Process. Syst., 2017
Int. J. Parallel Program., 2017
2015
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
2014
A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014
2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
2011
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011
A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics.
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
2010
A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics.
Proceedings of the IEEE 8th Symposium on Application Specific Processors, 2010