Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits. - Pei-Wen Luo; Jwu-E Chen; Chin-Long Wey; Liang-Chia Cheng; Ji-Jan Chen; Wen Ching Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Yield evaluation of analog placement with arbitrary capacitor ratio. - Jwu-E Chen; Pei-Wen Luo; Chin-Long Wey (ISQED, 2009)

Placement Optimization for Yield Improvement of Switched-Capacitor Analog Integrated Circuits. - Jwu-E Chen; Pei-Wen Luo; Chin-Long Wey (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Yield-award placement optimization for Switched-Capacitor analog integrated circuits. - Chien-Chih Huang; Jwu-E Chen; Pei-Wen Luo; Chin-Long Wey (SoCC, 2011)

Design Methodology for Yield Enhancement of Switched-Capacitor Analog Integrated Circuits. - Pei-Wen Luo; Jwu-E Chen; Chin-Long Wey (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Capturing the phantom of the power grid - on the runtime adaptive techniques for noise reduction. - Tao Wang; Pei-Wen Luo; Yu-Shih Su; Liang-Chia Cheng; Ding-Ming Kwai; Yiyu Shi 001 (ASP-DAC, 2012)

Reliable Power Delivery System Design for Three-Dimensional Integrated Circuits (3D ICs). - Pei-Wen Luo; Tao Wang; Chin-Long Wey; Liang-Chia Cheng; Bih-Lan Sheu; Yiyu Shi 001 (ISVLSI, 2012)

Benchmarking for research in power delivery networks of three-dimensional integrated circuits. - Pei-Wen Luo; Chun Zhang; Yung-Tai Chang; Liang-Chia Cheng; Hung-Hsie Lee; Bih-Lan Sheu; Yu-Shih Su; Ding-Ming Kwai; Yiyu Shi 001 (ISPD, 2013)

Optimal common-centroid-based unit capacitor placements for yield enhancement of switched-capacitor circuits. - Chien-Chih Huang; Chin-Long Wey; Jwu-E Chen; Pei-Wen Luo (ACM Trans. Design Autom. Electr. Syst., 2013)

Variation aware optimal threshold voltage computation for on-chip noise sensors. - Tao Wang; Chun Zhang; Jinjun Xiong; Pei-Wen Luo; Liang-Chia Cheng; Yiyu Shi 001 (ICCAD, 2014)

DArT: A Component-Based DRAM Area, Power, and Timing Modeling Tool. - Hsiu-Chuan Shih; Pei-Wen Luo; Jen-Chieh Yeh; Shu-Yen Lin; Ding-Ming Kwai; Shih-Lien Lu; Andre Schaefer; Cheng-Wen Wu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

A computer designed half Gb 16-channel 819Gb/s high-bandwidth and 10ns low-latency DRAM for 3D stacked memory devices using TSVs. - Pei-Wen Luo; Chi-Kang Chen; Yu-Hui Sung; Wei Wu 024; Hsiu-Chuan Shih; Chia-Hsin Lee; Kuo-Hua Lee; Ming-Wei Li; Mei-Chiang Lung; Chun-Nan Lu; Yung-Fa Chou; Po-Lin Shih; et al. (VLSIC, 2015)

Selective Body Biasing for Post-Silicon Tuning of Sub-Threshold Designs: An Adaptive Filtering Approach. - Hui Geng; Jianming Liu 001; Pei-Wen Luo; Liang-Chia Cheng; Steven L. Grant; Yiyu Shi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015)

Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs. - Chien-Chih Huang; Chin-Long Wey; Jwu-E Chen; Pei-Wen Luo (ACM Trans. Design Autom. Electr. Syst., 2015)

Selective body biasing for post-silicon tuning of sub-threshold designs: A semi-infinite programming approach with Incremental Hypercubic Sampling. - Hui Geng; Jianming Liu 001; Jinglan Liu; Pei-Wen Luo; Liang-Chia Cheng; Steven L. Grant; Yiyu Shi 001 (Integr., 2016)

On the Optimal Threshold Voltage Computation of On-Chip Noise Sensors. - Tao Wang; Chun Zhang; Jinjun Xiong; Pei-Wen Luo; Liang-Chia Cheng; Yiyu Shi 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)