Variation-resilient voltage generation for SRAM weak cell testing. - Chingwei Yeh; Yan-Nan Liu; Jinn-Shyan Wang; Pei-Yao Chang (ASICON, 2011)

Design of Subthreshold SRAMs for Energy-Efficient Quality-Scalable Video Applications. - Jinn-Shyan Wang; Pei-Yao Chang; Tai-Shin Tang; Jia-Wei Chen; Jiun-In Guo (IEEE J. Emerg. Sel. Topics Circuits Syst., 2011)

Design of 65 nm Sub-Threshold SRAM Using the Bitline Leakage Prediction Scheme and the Non-trimmed Sense Amplifier. - Jinn-Shyan Wang; Pei-Yao Chang; Chi-Chang Lin (IEICE Trans. Electron., 2012)

A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS. - Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Yen-Hsiang Yu (IEEE Trans. Circuits Syst. II Express Briefs, 2012)

A 0.48V 0.57nJ/pixel video-recording SoC in 65nm CMOS. - Tay-Jyi Lin; Cheng-An Chien; Pei-Yao Chang; Ching-Wen Chen; Po-Hao Wang; Ting-Yu Shyu; Chien-Yung Chou; Shien-Chun Luo; Jiun-In Guo; Tien-Fu Chen; Gene C. H. Chuang; Yuan-Hua Chu; et al. (ISSCC, 2013)

Variation-aware and adaptive-latency accesses for reliable low voltage caches. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (VLSI-SoC, 2013)

A Calibration-Free PVTD-Variation-Tolerant Sensing Scheme for Footless-8T SRAM Designs. - Jinn-Shyan Wang; Yung-Chen Chien; Fengzhi Liu; Pei-Yao Chang (IEEE Trans. Multi Scale Comput. Syst., 2015)

Zero-Counting and Adaptive-Latency Cache Using a Voltage-Guardband Breakthrough for Energy-Efficient Operations. - Po-Hao Wang; Wei-Chung Cheng; Yung-Hui Yu; Tang-Chieh Kao; Chi-Lun Tsai; Pei-Yao Chang; Tay-Jyi Lin; Jinn-Shyan Wang; Tien-Fu Chen (IEEE Trans. Circuits Syst. II Express Briefs, 2016)

Green Smart Campus Monitoring and Detection Using LoRa. - Kuo-Hsiung Tseng; Meng-Yun Chung; Li-Hsien Chen; Pei-Yao Chang (Sensors, 2021)