Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping. - Pei-Ying Chao; Chao-Wen Tzeng; Shi-Yu Huang; Chia-Chieh Weng; Shan-Chien Fang (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Parameterized All-Digital PLL Architecture and its Compiler to Support Easy Process Migration. - Chao-Wen Tzeng; Shi-Yu Huang; Pei-Ying Chao (IEEE Trans. Very Large Scale Integr. Syst., 2014)