A High Linearity 6th-order active R-MOSFET-C band-pass filter for power-line communication. - Di Zhu; Jiacheng Wang; Chaoli Zhong; Jie Tian; Yiming Tang; Peiyuan Wan; Ping Lin (APCCAS, 2010)

SHA-less pipelined ADC converting 10th Nyquist band with in-situ clock-skew calibration. - Pingli Huang; Szukang Hsien; Victor Lu; Peiyuan Wan; Seung-Chul Lee; Wenbo Liu 003; Bo-Wei Chen; Yung-Pin Lee; Wen-Tsao Chen; Tzu-Yi Yang; Gin-Kou Ma; Yun Chiu (CICC, 2010)

A 5.8-mW, 20-MHz, 4th-order programmable elliptic filter achieving over -80-dB IM3. - Peiyuan Wan; Yun Chiu; Pingfen Lin (CICC, 2010)

A 1.2-V 250-MS/s 8-bit pipelined ADC in 0.13-µm CMOS. - Peiyuan Wan; Wei Lang 003; Di Fang 001; Wei Cui; Pingfen Lin (ASICON, 2011)

A 48-mW, 12-bit, 150-MS/s pipelined ADC with digital calibration in 65nm CMOS. - Bei Peng; Guanzhong Huang; Hao Li 001; Peiyuan Wan; Pingfen Lin (CICC, 2011)

SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration. - Pingli Huang; Szukang Hsien; Victor Lu; Peiyuan Wan; Seung-Chul Lee; Wenbo Liu 003; Bo-Wei Chen; Yung-Pin Lee; Wen-Tsao Chen; Tzu-Yi Yang; Gin-Kou Ma; Yun Chiu (IEEE J. Solid State Circuits, 2011)

A 0.8 V 48 μW 82 dB SNDR 10-kHz BANDWIDTH ΣΔ MODULATOR IN 0.13-μM CMOS. - Wei Lang 003; Peiyuan Wan; Pingfen Lin (J. Circuits Syst. Comput., 2013)

A digitally calibrated low-power ring oscillator. - Ming Li; Haibin Yin; Peiyuan Wan (ASICON, 2015)

DCPG: Double-control power gating technique for a 28 nm Cortex™-A9 MPCore Quad-core processor. - Qian Liang; Jinhui Wang; Peiyuan Wan; Ligang Hou; Na Gong (ASICON, 2015)

Design and testing of CMOS compatible EEPROM. - Haibin Yin; Xiaohong Peng; Peiyuan Wan; Jinhui Wang; Ligang Hou (ASICON, 2015)

Non-Ideal Issues Analysis in a Fully Passive Noise Shaping SAR ADC. - Zhijie Chen; Peiyuan Wan; Ning Li (IEICE Trans. Electron., 2019)

A 4x folding voltage-to-time converter with adjustable conversion gain and offset for time-based ADC. - Yucheng Bao; Zhijie Chen; Boyong Jin; Peiyuan Wan (ASICON, 2021)

A 4.39ps, 1.5GS/s Time-to-Digital Converter with 4× Phase Interpolation Technique and a 2-D Quantization Array. - Yongkuo Ma; Peiyuan Wan; Hongda Zhang; Zhi Wan; Xiaoyu Zhang; Xu Liu 008; Zhijie Chen (A-SSCC, 2021)

Design of an Exponential Current Generator for Neural Stimulation. - Juzhe Li; Xu Liu; Peiyuan Wan; Zhijie Chen (ICTA, 2021)

A 1.65 mW 2.8 GHz Dual-Loops Class-C VCO Achieving 189 dBc/Hz FoM. - Qianshui Yu; Chuankai Wang; Zijing Yuan; Xu Liu 002; Peiyuan Wan; Zhijie Chen (ICTA, 2021)

A Low-Noise Neural Signal Amplifier Achieving 1.6 NEF and 2.56 PEF for Brain-Machine Interface. - Weijian Chen; Xu Liu 008; Weisong Liang; Zeyu Lu; Peiyuan Wan; Zhijie Chen (APCCAS, 2022)

A 4-Channel Neural Stimulation IC Design with Charge Balancing and Exponential Current Output. - Juzhe Li; Xu Liu 008; Peiyuan Wan; Zhijie Chen (APCCAS, 2022)

A Wireless Power Design with High PCE and Fast Transient Response over a Large Loading Range for Multi-channel Neural Stimulators. - Weisong Liang; Xu Liu 008; Weijian Chen; Zeyu Lu; Peiyuan Wan; Zhijie Chen (APCCAS, 2022)

A Neural Recording IC Design with on-chip CMOS Electrode Array for Brain-machine Interface. - Ronghao Zhang; Xu Liu 008; Zhijie Chen; Peiyuan Wan; Tao Chen (APCCAS, 2022)

Energy-efficient Fe-based FET logic in LUT circuit with transistor reduction technique. - Zhijie Chen; Yu Zhang; Zhiyuan Gao; Peiyuan Wan (IEICE Electron. Express, 2022)

A 8-bit, 1-GHz coarse-fine time-based ADC with split-CDAC residue transfer. - Peiyuan Wan; Yucheng Bao; Boyong Jin; Zhijie Chen (IEICE Electron. Express, 2022)

A Bio-Impedance Measurement Chip Design with AC Current Outputs. - Xu Liu 008; Yukun Jiao; Zeyu Lu; Weijian Chen; Peiyuan Wan; Zhijie Chen (ICTA, 2023)

A Fast Bioimpedance Measurement Chip Design Using Dynamic Current. - Xu Liu; Yukun Jiao; Zeyu Lu; Weijian Chen; Peiyuan Wan; Zhijie Chen (ICTA, 2023)

A 1.9-ps 8× phase interpolation TDC for time-based analog-to-digital converter with capacitance compensation self-calibration. - Zhijie Chen; Xiaoyu Zhang; Yongkuo Ma; Xitong Liang; Xinyu Du; Peiyuan Wan (IEICE Electron. Express, 2023)

A Low Noise Neural Recording Frontend IC With Power Management for Closed-Loop Brain-Machine Interface Application. - Weijian Chen; Weisong Liang; Xu Liu 002; Zeyu Lu; Peiyuan Wan; Zhijie Chen (IEEE Trans. Biomed. Circuits Syst., 2023)

A 4-Channel Neural Stimulation IC Design With Charge Balancing and Multiple Current Output Modes. - Juzhe Li; Weijian Chen; Xu Liu 002; Peiyuan Wan; Zhijie Chen (IEEE Trans. Biomed. Circuits Syst., 2023)

Design of analog front-end integrated circuit of tactile sensor for human-machine interface. - Zheng Wang; Xu Liu 002; Yunao Chen; Qiumeng Fan; Zhijie Chen; Peiyuan Wan (Integr., 2023)

A 4x16 Arrayed Current Sensing Front-End Chip for DNA Sequencing. - Xu Liu; Yuzhou Huang; Qiumeng Fan; Yunao Chen; Zhijie Chen; Peiyuan Wan (ICTA, 2024)

A Capacitor-Less LDO Regulator Compensated by Adaptive Zero for Zero-Load Stability Enhancement. - Shengping Lv; Zhijie Chen; Peng Zhang; Peiyuan Wan; Liuxin Lv; Hanjun Jiang (ISCAS, 2024)

A fast-response RBCOT buck converter with second-order differential and integrator compensation based on FVF. - Sujuan Liu; Kun Liu; Zifeng Xing; Aoran Ge; Peiyuan Wan (Microelectron. J., 2024)

A PN-complementary current-enhancement structure LDO with fast transient response and frequency compensation capability. - Sujuan Liu; Aoran Ge; Xudong Sun 017; Junchao Zhao; Kun Liu; Peiyuan Wan (Microelectron. J., 2025)

A Novel Energy Efficient Single-Capacitor Switching Scheme for SAR ADCs. - Bingjie Li; Peiyuan Wan; Xu Liu 002; Zhijie Chen; Sujuan Liu (IEEE Signal Process. Lett., 2025)

PttAcc: Pipeline-Based Taylor Expansion Fitting Arctangent Angle Hardware Accelerator Design for Descriptor Duty in ORB-SLAM System. - Meng Liu 018; Fei Xiao; Ruijie Wang; Peiyuan Wan; Zhijie Chen; Dejian Li; Chongfei Shen (IEEE Embed. Syst. Lett., 2025)

FPGA Implementation of Staged Projection Refining Multiple Orthogonal Matching Pursuit Algorithm for Compressed Sensing. - Sujuan Liu; Yichen Liang; Zixing Zhang 007; Peiyuan Wan (IEEE Trans. Very Large Scale Integr. Syst., 2025)