A Highly-Reliable and Energy-Efficient Physical Unclonable Function Based on 4T All-MOSFET Subthreshold Voltage Reference. - Peizhou Gan; Yiheng Wu; Yuan Cao 003; Xiaojin Zhao (AsianHOST, 2019)

A 124 fJ/Bit Cascode Current Mirror Array Based PUF With 1.50% Native Unstable Bit Ratio. - Xiaojin Zhao; Peizhou Gan; Qiang Zhao; Dejian Liang; Yuan Cao 003; Xiaofang Pan; Amine Bermak (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

An All-MOSFET Voltage Reference-Based PUF Featuring Low BER Sensitivity to VT Variations and 163 fJ/Bit in 180-nm CMOS. - Peizhou Gan; Xiaojin Zhao; Yuan Cao 003 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation. - Aneesh Kandi; Anubhab Baksi; Peizhou Gan; Sylvain Guilley; Tomas Gerlich; Jakub Breier; Anupam Chattopadhyay; Ritu Ranjan Shrivastwa; Zdenek Martinasek; Shivam Bhasin (ISVLSI, 2024)

Classic McEliece Hardware Implementation with Enhanced Side-Channel and Fault Resistance. - Peizhou Gan; Prasanna Ravi; Kamal Raj; Anubhab Baksi; Anupam Chattopadhyay (IACR Cryptol. ePrint Arch., 2024)

Side-Channel and Fault Resistant ASCON Implementation: A Detailed Hardware Evaluation (Extended Version). - Aneesh Kandi; Anubhab Baksi; Peizhou Gan; Sylvain Guilley; Tomas Gerlich; Jakub Breier; Anupam Chattopadhyay; Ritu Ranjan Shrivastwa; Zdenek Martinasek; Shivam Bhasin (IACR Cryptol. ePrint Arch., 2024)