Loop Scheduling for Transport Triggered Architecture Processors. - Perttu Salmela; Risto Mäkinen; Pekka Jääskeläinen; Jarmo Takala (SoC, 2006)

Software Pipelining Support for Transport Triggered Architecture Processors. - Perttu Salmela; Pekka Jääskeläinen; Tuomas Järvinen; Jarmo Takala (SAMOS, 2006)

Run-Time Scheduled Hardware Acceleration of MPEG-4 Video Decoding. - Jani Boutellier; Pekka Jääskeläinen; Olli Silvén (SoC, 2007)

Resource Conflict Detection in Simulation of Function Unit Pipelines. - Pekka Jääskeläinen; Vladimír Guzma; Jarmo Takala (SAMOS, 2007)

Reducing Context Switch Overhead with Compiler-Assisted Threading. - Pekka Jääskeläinen; Pertti Kellomäki; Jarmo Takala; Heikki Kultala; Mikael Lepistö (EUC (2), 2008)

Impact of Software Bypassing on Instruction Level Parallelism and Register File Traffic. - Vladimír Guzma; Pekka Jääskeläinen; Pertti Kellomäki; Jarmo Takala (SAMOS, 2008)

Resource conflict detection in simulation of function unit pipelines. - Pekka Jääskeläinen; Vladimír Guzma; Viljami Korhonen (J. Syst. Archit., 2008)

Programmable and Scalable Architecture for Graphics Processing Units. - Carlos S. de La Lama; Pekka Jääskeläinen; Jarmo Takala (SAMOS, 2009)

Programmable Accelerators for Reconfigurable Video Decoder. - Tero Rintaluoma; Timo Reinikka; Joona Rouvinen; Jani Boutellier; Pekka Jääskeläinen; Olli Silvén (SAMOS, 2009)

Reconfigurable video decoder with transform acceleration. - Lassi Nurmi; Perttu Salmela; Pertti Kellomäki; Pekka Jääskeläinen; Jarmo Takala (SiPS, 2009)

Customized Exposed Datapath Soft-Core Design Flow with Compiler Support. - Otto Esko; Pekka Jääskeläinen; Pablo Huerta; Carlos S. de La Lama; Jarmo Takala; José Ignacio Martínez (FPL, 2010)

OpenCL-based design methodology for application-specific processors. - Pekka Jääskeläinen; Carlos S. de La Lama; Pablo Huerta; Jarmo Takala (ICSAMOS, 2010)

Operation set customization in retargetable compilers. - Heikki Kultala; Pekka Jääskeläinen; Jarmo Takala (ACSCC, 2011)

Customizable Datapath Integrated Lock Unit. - Pekka Jääskeläinen; Erno Salminen; Otto Esko; Jarmo Takala (SoC, 2011)

TCEMC: A co-design flow for application-specific multicores. - Pekka Jääskeläinen; Erno Salminen; Carlos S. de La Lama; Jarmo Takala; José Ignacio Martínez (ICSAMOS, 2011)

Design Methodology for Offloading Software Executions to FPGA. - Tomasz Patyk; Perttu Salmela; Teemu Pitkänen; Pekka Jääskeläinen; Jarmo Takala (J. Signal Process. Syst., 2011)

From Parallel Programs to Customized Parallel Processors. - Pekka Jääskeläinen (2012)

Simplified floating-point division and square root. - Timo Viitanen; Pekka Jääskeläinen; Otto Esko; Jarmo Takala (ICASSP, 2013)

Towards run-time actor mapping of dynamic dataflow programs onto multi-core platforms. - Hervé Yviquel; Emmanuel Casseau; Mickaël Raulet; Pekka Jääskeläinen; Jarmo Takala (ISPA, 2013)

A 122Mb/s Turbo decoder using a mid-range GPU. - Xianjun Jiao; Canfeng Chen; Pekka Jääskeläinen; Vladimír Guzma; Heikki Berg (IWCMC, 2013)

Turbo decoding on tailored OpenCL processor. - Heikki Kultala; Otto Esko; Pekka Jääskeläinen; Vladimír Guzma; Jarmo Takala; Xianjun Jiao; Tommi Zetterman; Heikki Berg (IWCMC, 2013)

Special session on "Exposed data path architectures: Recent advances and applications". - Jani Boutellier; Pekka Jääskeläinen (ICSAMOS, 2013)

Low-power application-specific FFT processor for LTE applications. - Tomasz Patyk; David Guevorkian; Teemu Pitkänen; Pekka Jääskeläinen; Jarmo Takala (ICSAMOS, 2013)

Inexpensive correctly rounded floating-point division and square root with input scaling. - Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (SiPS, 2013)

Heuristics for greedy transport triggered architecture interconnect exploration. - Timo Viitanen; Heikki Kultala; Pekka Jääskeläinen; Jarmo Takala (CASES, 2014)

Parallel programming of a symmetric transport-triggered architecture with applications in flexible LDPC encoding. - Blaine Rister; Pekka Jääskeläinen; Olli Silvén; Jari Hannuksela; Joseph R. Cavallaro (ICASSP, 2014)

A high throughput LDPC decoder using a mid-range GPU. - Xie Wen; Xianjun Jiao; Pekka Jääskeläinen; Heikki Kultala; Canfeng Chen; Heikki Berg; Zhisong Bie (ICASSP, 2014)

Efficient software synthesis of dynamic dataflow programs. - Hervé Yviquel; Alexandre Sanchez; Pekka Jääskeläinen; Jarmo Takala; Mickaël Raulet; Emmanuel Casseau (ICASSP, 2014)

Grover: Looking for Performance Improvement by Disabling Local Memory Usage in OpenCL Kernels. - Jianbin Fang; Henk J. Sips; Pekka Jääskeläinen; Ana Lucia Varbanescu (ICPP, 2014)

Programmable in-loop deblock filter processor for video decoders. - Janne Janhunen; Pekka Jääskeläinen; Jari Hannuksela; Tero Rintaluoma; Aki Kuusela (SiPS, 2014)

Compiler optimizations for code density of variable length instructions. - Heikki Kultala; Timo Viitanen; Pekka Jääskeläinen; Janne Helkala; Jarmo Takala (SiPS, 2014)

Parallel processing intensive digital front-end for IEEE 802.11ac receiver. - Mona Aghababaee Tafreshi; Juha Yli-Kaakinen; Toni Levanen; Ville Korhonen; Pekka Jääskeläinen; Markku Renfors; Mikko Valkama; Jarmo Takala (ACSSC, 2015)

Rapid customization of image processors using Halide. - Ville Korhonen; Pekka Jääskeläinen; Matias Koskela; Timo Viitanen; Jarmo Takala (GlobalSIP, 2015)

Power optimizations for transport triggered SIMD processors. - Joonas Multanen; Timo Viitanen; Henry Linjamaki; Heikki Kultala; Pekka Jääskeläinen; Jarmo Takala; Lauri Koskinen; Jesse Simonsson; Heikki Berg; Kalle Raiskila; Tommi Zetterman (SAMOS, 2015)

MergeTree: a HLBVH constructor for mobile systems. - Timo Viitanen; Matias Koskela; Pekka Jääskeläinen; Heikki Kultala; Jarmo Takala (SIGGRAPH Asia Technical Briefs, 2015)

pocl: A Performance-Portable OpenCL Implementation. - Pekka Jääskeläinen; Carlos Sánchez de La Lama; Erik Schnetter; Kalle Raiskila; Jarmo Takala; Heikki Berg (Int. J. Parallel Program., 2015)

Data Intensive Computing: From Modeling to Implementation. - Pekka Jääskeläinen; Jani Boutellier (J. Signal Process. Syst., 2015)

Code Density and Energy Efficiency of Exposed Datapath Architectures. - Pekka Jääskeläinen; Heikki Kultala; Timo Viitanen; Jarmo Takala (J. Signal Process. Syst., 2015)

Embedded Multi-Core Systems Dedicated to Dynamic Dataflow Programs. - Hervé Yviquel; Alexandre Sanchez; Pekka Jääskeläinen; Jarmo Takala; Mickaël Raulet; Emmanuel Casseau (J. Signal Process. Syst., 2015)

Software defined radio implementation of adaptive nonlinear digital self-interference cancellation for mobile inband full-duplex radio. - Mona Aghababaeetafreshi; Matias Koskela; Dani Korpi; Pekka Jääskeläinen; Mikko Valkama; Jarmo Takala (GlobalSIP, 2016)

Half-precision Floating-point Ray Traversal. - Matias Koskela; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (VISIGRAPP (1: GRAPP), 2016)

Customized high performance low power processor for binaural speaker localization. - Nicolai Behmann; Christopher Seifert; Guillermo Payá-Vayá; Holger Blume; Pekka Jääskeläinen; Joonas Multanen; Heikki Kultala; Jarmo Takala; Joachim Thiemann; Steven van de Par (ICECS, 2016)

Foveated Path Tracing - A Literature Review and a Performance Gain Analysis. - Matias Koskela; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (ISVC (1), 2016)

OpenCL programmable exposed datapath high performance low-power image signal processor. - Joonas Multanen; Heikki Kultala; Matias Koskela; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala; Aram Danielyan; Cristóvão Cruz (NORCAS, 2016)

Aggressively bypassing list scheduler for transport triggered architectures. - Heikki O. Kultala; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (SAMOS, 2016)

Multi bounding volume hierarchies for ray tracing pipelines. - Timo Viitanen; Matias Koskela; Pekka Jääskeläinen; Jarmo Takala (SIGGRAPH Asia Technical Briefs, 2016)

Xor-Masking: A Novel Statistical Method for Instruction Read Energy Reduction in Contemporary SRAM Technologies. - Joonas Multanen; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (SiPS, 2016)

Integer Linear Programming-Based Scheduling for Transport Triggered Architectures. - Tomi Äijö; Pekka Jääskeläinen; Tapio Elomaa; Heikki Kultala; Jarmo Takala (ACM Trans. Archit. Code Optim., 2016)

Improving Code Density with Variable Length Encoding Aware Instruction Scheduling. - Heikki Kultala; Timo Viitanen; Pekka Jääskeläinen; Janne Helkala; Jarmo Takala (J. Signal Process. Syst., 2016)

Exposed datapath optimizations for loop scheduling. - Heikki O. Kultala; Pekka Jääskeläinen; Johannes IJzerman; Lasse Lehtonen; Timo Viitanen; Markku J. Mäkitalo; Jarmo H. Takala (SAMOS, 2017)

Foveated instant preview for progressive rendering. - Matias Koskela; Kalle Immonen; Timo Viitanen; Pekka Jääskeläinen; Joonas Multanen; Jarmo Takala (SIGGRAPH Asia Technical Briefs, 2017)

Fast Hardware Construction and Refitting of Quantized Bounding Volume Hierarchies. - Timo Viitanen; Matias Koskela; Pekka Jääskeläinen; Kalle Immonen; Jarmo Takala (Comput. Graph. Forum, 2017)

MergeTree: A Fast Hardware HLBVH Constructor for Animated Ray Tracing. - Timo Viitanen; Matias Koskela; Pekka Jääskeläinen; Heikki Kultala; Jarmo Takala (ACM Trans. Graph., 2017)

Codesign Case Study on Transport-Triggered Architectures. - Jarmo Takala; Pekka Jääskeläinen; Teemu Pitkänen (Handbook of Hardware/Software Codesign, 2017)

Sparse Sampling for Real-time Ray Tracing. - Timo Viitanen; Matias Koskela; Kalle Immonen; Markku J. Mäkitalo; Pekka Jääskeläinen; Jarmo Takala (VISIGRAPP (1: GRAPP), 2018)

Transport-Triggered Soft Cores. - Pekka Jääskeläinen; Aleksi Tervo; Guillermo Payá Vayá; Timo Viitanen; Nicolai Behmann; Jarmo Takala; Holger Blume (IPDPS Workshops, 2018)

Transport Triggered Polar Decoders. - Mathieu Léonardon; Camille Leroux; Pekka Jääskeläinen; Christophe Jégo; Yvon Savaria (ISTC, 2018)

Energy-Delay Trade-Offs in Instruction Register File Design. - Joonas Multanen; Heikki Kultala; Pekka Jääskeläinen (NORCAS, 2018)

AivoTTA: an energy efficient programmable accelerator for CNN-based object recognition. - Jos IJzerman; Timo Viitanen; Pekka Jääskeläinen; Heikki Kultala; Lasse Lehtonen; Maurice Peemen; Henk Corporaal; Jarmo Takala (SAMOS, 2018)

LoTTA: Energy-Efficient Processor for Always-On Applications. - Joonas Multanen; Heikki Kultala; Pekka Jääskeläinen; Timo Viitanen; Aleksi Tervo; Jarmo Takala (SiPS, 2018)

Offloading C++17 Parallel STL on System Shared Virtual Memory Platforms. - Pekka Jääskeläinen; John Glossner; Martin Jambor; Aleksi Tervo; Matti Rintala (ISC Workshops, 2018)

Instantaneous foveated preview for progressive Monte Carlo rendering. - Matias Koskela; Kalle Immonen; Timo Viitanen; Pekka Jääskeläinen; Joonas Multanen; Jarmo H. Takala (Comput. Vis. Media, 2018)

Variable Length Instruction Compression on Transport Triggered Architectures. - Timo Viitanen; Janne Helkala; Heikki Kultala; Pekka Jääskeläinen; Jarmo Takala; Tommi Zetterman; Heikki Berg (Int. J. Parallel Program., 2018)

PLOCTree: A Fast, High-Quality Hardware BVH Builder. - Timo Viitanen; Matias Koskela; Pekka Jääskeläinen; Aleksi Tervo; Jarmo Takala (Proc. ACM Comput. Graph. Interact. Tech., 2018)

Software Defined Radio Implementation of a Digital Self-interference Cancellation Method for Inband Full-Duplex Radio Using Mobile Processors. - Mona Aghababaeetafreshi; Dani Korpi; Matias Koskela; Pekka Jääskeläinen; Mikko Valkama; Jarmo Takala (J. Signal Process. Syst., 2018)

Instruction Fetch Energy Reduction with Biased SRAMs. - Joonas Multanen; Timo Viitanen; Pekka Jääskeläinen; Jarmo Takala (J. Signal Process. Syst., 2018)

The FitOptiVis ECSEL project: highly efficient distributed embedded image/video processing in cyber-physical systems. - Zaid Al-Ars; Twan Basten; Ad de Beer; Marc Geilen; Dip Goswami; Pekka Jääskeläinen; Jirí Kadlec; Marcos Martinez de Alejandro; Francesca Palumbo; Geran Peeren; Luigi Pomante; Frank van der Linden 001; et al. (CF, 2019)

AEx: Automated Customization of Exposed Datapath Soft-Cores. - Alex Hirvonen; Kati Tervo; Heikki Kultala; Pekka Jääskeläinen (DSD, 2019)

Reducing Computational Complexity of Real-Time Stereoscopic Ray Tracing with Spatiotemporal Sample Reprojection. - Markku J. Mäkitalo; Petrus E. J. Kivi; Matias Koskela; Pekka Jääskeläinen (VISIGRAPP (1: GRAPP), 2019)

SHRIMP: Efficient Instruction Delivery with Domain Wall Memory. - Joonas Multanen; Pekka Jääskeläinen; Asif Ali Khan; Fazal Hameed; Jerónimo Castrillón (ISLPED, 2019)

Foveated Real-Time Path Tracing in Visual-Polar Space. - Matias Koskela; Atro Lotvonen; Markku J. Mäkitalo; Petrus E. J. Kivi; Timo Viitanen; Pekka Jääskeläinen (EGSR (DL/I), 2019)

Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments. - Sven Gesper; Moritz Weißbrich; Stephan Nolting; Tobias Stuckenberg; Pekka Jääskeläinen; Holger Blume; Guillermo Payá-Vayá (SAMOS, 2019)

Towards Efficient Code Generation for Exposed Datapath Architectures. - Kanishkan Vadivel; Roel Jordans; Sander Stuijk; Henk Corporaal; Pekka Jääskeläinen; Heikki Kultala (SCOPES, 2019)

Programmable and Scalable Architecture for Graphics Processing Units. - Carlos S. de La Lama; Pekka Jääskeläinen; Heikki Kultala; Jarmo Takala (Trans. High Perform. Embed. Archit. Compil., 2019)

Blockwise Multi-Order Feature Regression for Real-Time Path-Tracing Reconstruction. - Matias Koskela; Kalle Immonen; Markku J. Mäkitalo; Alessandro Foi; Timo Viitanen; Pekka Jääskeläinen; Heikki Kultala; Jarmo Takala (ACM Trans. Graph., 2019)

LordCore: Energy-Efficient OpenCL-Programmable Software-Defined Radio Coprocessor. - Heikki Kultala; Timo Viitanen; Heikki Berg; Pekka Jääskeläinen; Joonas Multanen; Mikko Kokkonen; Kalle Raiskila; Tommi Zetterman; Jarmo Takala (IEEE Trans. Very Large Scale Integr. Syst., 2019)

ALMARVI System Solution for Image and Video Processing in Healthcare, Surveillance and Mobile Applications. - Zaid Al-Ars; Steven van der Vlugt; Pekka Jääskeläinen; Frank van der Linden 001 (J. Signal Process. Syst., 2019)

Exploiting Task Parallelism with OpenCL: A Case Study. - Pekka Jääskeläinen; Ville Korhonen; Matias Koskela; Jarmo Takala; Karen O. Egiazarian; Aram Danielyan; Cristóvão Cruz; James Price; Simon McIntosh-Smith (J. Signal Process. Syst., 2019)

Design and management of image processing pipelines within CPS: 2 years of experience from the FitOptiVis ECSEL Project. - Luigi Pomante; Francesca Palumbo; Claudia Rinaldi; Giacomo Valente; Carlo Sau; Tiziana Fanni; Frank van der Linden 001; Twan Basten; Marc Geilen; Geran Peeren; Jirí Kadlec; Pekka Jääskeläinen; et al. (DSD, 2020)

TTA-SIMD Soft Core Processors. - Kati Tervo; Samawat Malik; Topi Leppänen; Pekka Jääskeläinen (FPL, 2020)

Machine Learning is the Solution Also for Foveated Path Tracing Reconstruction. - Atro Lotvonen; Matias Koskela; Pekka Jääskeläinen (VISIGRAPP (1: GRAPP), 2020)

Programmable Dictionary Code Compression for Instruction Stream Energy Efficiency. - Joonas Multanen; Kari Hepola; Pekka Jääskeläinen (ICCD, 2020)

CPSoSaware: Cross-Layer Cognitive Optimization Tools & Methods for the Lifecycle Support of Dependable CPSoS. - Georgios Keramidas; Christos P. Antonopoulos; Nikolaos S. Voros; Pekka Jääskeläinen; Marisa Catalán Cid; Evangelia I. Zacharaki; Apostolos P. Fournaris; Aris S. Lalos (ISVLSI, 2020)

HIPCL: Tool for Porting CUDA Applications to Advanced OpenCL Platforms Through HIP. - Michal Babej; Pekka Jääskeläinen (IWOCL, 2020)

POCL-R: Distributed OpenCL Runtime for Low Latency Remote Offloading. - Jan Solanti; Michal Babej; Julius Ikkala; Pekka Jääskeläinen (IWOCL, 2020)

System Simulation of Memristor Based Computation in Memory Platforms. - Ali BanaGozar; Kanishkan Vadivel; Joonas Multanen; Pekka Jääskeläinen; Sander Stuijk; Henk Corporaal (SAMOS, 2020)

Systematic Evaluation of the Quality Benefits of Spatiotemporal Sample Reprojection in Real-Time Stereoscopic Path Tracing. - Markku J. Mäkitalo; Petrus E. J. Kivi; Pekka Jääskeläinen (IEEE Access, 2020)

Energy Efficient Low Latency Multi-issue Cores for Intelligent Always-On IoT Applications. - Joonas Multanen; Heikki Kultala; Kati Tervo; Pekka Jääskeläinen (J. Signal Process. Syst., 2020)

DDISH-GI: Dynamic Distributed Spherical Harmonics Global Illumination. - Julius Ikkala; Petrus E. J. Kivi; Joel Alanko; Markku J. Mäkitalo; Pekka Jääskeläinen (CGI, 2021)

Performance of Texture Compression Algorithms in Low-Latency Computer Vision Tasks. - Jakub Zádník; Markku J. Mäkitalo; Jussi Iho; Pekka Jääskeläinen (EUVIP, 2021)

Energy Efficient Multistandard Decompressor ASIP. - Joost Hoozemans; Kati Tervo; Pekka Jääskeläinen; Zaid Al-Ars (ICCDE, 2021)

Unified OpenCL Integration Methodology for FPGA Designs. - Topi Leppänen; Panagiotis Mousouliotis; Georgios Keramidas; Joonas Multanen; Pekka Jääskeläinen (NorCAS, 2021)

PoCL-R: A Scalable Low Latency Distributed OpenCL Runtime. - Jan Solanti; Michal Babej; Julius Ikkala; Vinod Kumar Malamal Vadakital; Pekka Jääskeläinen (SAMOS, 2021)

Evaluation of Different Processor Architecture Organizations for On-Site Electronics in Harsh Environments. - Sven Gesper; Moritz Weißbrich; Tobias Stuckenberg; Pekka Jääskeläinen; Holger Blume; Guillermo Payá-Vayá (Int. J. Parallel Program., 2021)

Design and management of image processing pipelines within CPS: Acquired experience towards the end of the FitOptiVis ECSEL Project. - Carlo Sau; Claudia Rinaldi; Luigi Pomante; Francesca Palumbo; Giacomo Valente; Tiziana Fanni; Marcos Martinez de Alejandro; Frank van der Linden 001; Twan Basten; Marc Geilen; Geran Peeren; Jirí Kadlec; et al. (Microprocess. Microsystems, 2021)

Dual-IS: Instruction Set Modality for Efficient Instruction Level Parallelism. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (ARCS, 2022)

OpenASIP 2.0: Co-Design Toolset for RISC-V Application-Specific Instruction-Set Processors. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (ASAP, 2022)

Real-Time Light Field Path Tracing. - Markku J. Mäkitalo; Erwan Leria; Julius Ikkala; Pekka Jääskeläinen (CGI, 2022)

Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures. - Kanishkan Vadivel; Barry de Bruin; Roel Jordans; Henk Corporaal; Pekka Jääskeläinen (DSD, 2022)

TauBench: Dynamic Benchmark for Graphics Rendering. - Joel Alanko; Markku J. Mäkitalo; Pekka Jääskeläinen (VISIGRAPP (1: GRAPP), 2022)

Pruned Lightweight Encoders for Computer Vision. - Jakub Zádník; Markku J. Mäkitalo; Pekka Jääskeläinen (MMSP, 2022)

Tauray: A Scalable Real-Time Open-Source Path Tracer for Stereo and Light Field Displays. - Julius Ikkala; Markku J. Mäkitalo; Tuomas Lauttia; Erwan Leria; Pekka Jääskeläinen (SIGGRAPH Asia Technical Communications, 2022)

Real-Time Rendering of Point Clouds With Photorealistic Effects: A Survey. - Petrus E. J. Kivi; Markku J. Mäkitalo; Jakub Zádník; Julius Ikkala; Vinod Kumar Malamal Vadakital; Pekka Jääskeläinen (IEEE Access, 2022)

BrainTTA: A 35 fJ/op Compiler Programmable Mixed-Precision Transport-Triggered NN SoC. - Maarten Molendijk; Floran de Putter; Manil Dev Gomony; Pekka Jääskeläinen; Henk Corporaal (CoRR, 2022)

Cross-vendor programming abstraction for diverse heterogeneous platforms. - Topi Leppänen; Atro Lotvonen; Pekka Jääskeläinen (Frontiers Comput. Sci., 2022)

Energy-Efficient Instruction Delivery in Embedded Systems With Domain Wall Memory. - Joonas Multanen; Kari Hepola; Asif Ali Khan; Jerónimo Castrillón; Pekka Jääskeläinen (IEEE Trans. Computers, 2022)

Image and Video Coding Techniques for Ultra-low Latency. - Jakub Zádník; Markku J. Mäkitalo; Jarno Vanne; Pekka Jääskeläinen (ACM Comput. Surv., 2022)

On the OpenCL Support for Streaming Fixed-Function Accelerators on Embedded SoC FPGAs. - Panagiotis Mousouliotis; Topi Leppänen; Pekka Jääskeläinen; Nikos Petrellis; Panagiotis Christakos; Georgios Keramidas; Christos P. Antonopoulos; Nikolaos S. Voros (ARC, 2023)

BrainTTA: A 28.6 TOPS/W Compiler Programmable Transport-Triggered NN SoC. - Maarten J. Molendijk; Floran A. M. de Putter; Manil Dev Gomony; Pekka Jääskeläinen; Henk Corporaal (ICCD, 2023)

Open Standard Software Stack for Low Latency Offloading from Lightweight Devices to Remote Heterogeneous Platforms. - Jan Solanti; Topi Leppänen; Pekka Jääskeläinen (IWOCL, 2023)

AFOCL: Portable OpenCL Programming of FPGAs via Automated Built-in Kernel Management. - Topi Leppänen; Joonas Multanen; Leevi Leppänen; Pekka Jääskeläinen (NorCAS, 2023)

TauBench 1.1: A Dynamic Benchmark for Graphics Rendering. - Erfan Momeni Yazdi; Markku J. Mäkitalo; Julius Ikkala; Pekka Jääskeläinen (CoRR, 2023)

PoCL-R: An Open Standard Based Offloading Layer for Heterogeneous Multi-Access Edge Computing with Server Side Scalability. - Jan Solanti; Michal Babej; Julius Ikkala; Pekka Jääskeläinen (CoRR, 2023)

Efficient OpenCL system integration of non-blocking FPGA accelerators. - Topi Leppänen; Atro Lotvonen; Panagiotis Mousouliotis; Joonas Multanen; Georgios Keramidas; Pekka Jääskeläinen (Microprocess. Microsystems, 2023)

AEx: Automated High-Level Synthesis of Compiler Programmable Co-Processors. - Alex Hirvonen; Topi Leppänen; Kari Hepola; Joonas Multanen; Joost Hoozemans; Pekka Jääskeläinen (J. Signal Process. Syst., 2023)

Towards Efficient OpenCL Pipe Specification for Hardware Accelerators. - Topi Leppänen; Joonas Multanen; Leevi Leppänen; Pekka Jääskeläinen (IWOCL, 2024)

Fully Automatic Compiler Retargeting and CV-X-IF Hardware Interface Generation for RISC-V Custom Instructions. - Kari Hepola; Tharaka Ranasinghe Arachchige; Joonas Multanen; Pekka Jääskeläinen (NorCAS, 2024)

Cycle Count Estimation of VLIW Processors Using Machine Learning. - Kari Hepola; Jatan Shrestha; Joonas Multanen; Vivienne Wang; Joni Pajarinen; Pekka Jääskeläinen (NorCAS, 2024)

k-DOP Clipping: Robust Ghosting Mitigation in Temporal Antialiasing. - Julius Ikkala; Tuomas Lauttia; Pekka Jääskeläinen; Markku J. Mäkitalo (SIGGRAPH Asia Technical Communications, 2024)

Hierarchical Bitmask Implicit Grids for Efficient Point-in-Volume Queries on the GPU. - Julius Ikkala; Tuomas Lauttia; Pekka Jääskeläinen; Markku J. Mäkitalo (VISIGRAPP (1): GRAPP, HUCAPP, IVAPP, 2024)

Interactive Multi-GPU Light Field Path Tracing Using Multi-Source Spatial Reprojection. - Erwan Leria; Markku J. Mäkitalo; Pekka Jääskeläinen; Mårten Sjöström; Tingting Zhang (VRST, 2024)

Performance of Linear Coding and Transmission in Low-Latency Computer Vision Offloading. - Jakub Zádník; Anthony Trioux; Michel Kieffer; Markku J. Mäkitalo; François-Xavier Coudoux; Patrick Corlay; Pekka Jääskeläinen (WCNC, 2024)

Energy-Efficient Exposed Datapath Architecture With a RISC-V Instruction Set Mode. - Kari Hepola; Joonas Multanen; Pekka Jääskeläinen (IEEE Trans. Computers, 2024)

R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA. - Barry de Bruin; Kanishkan Vadivel; Mark Wijtvliet; Pekka Jääskeläinen; Henk Corporaal (ACM Trans. Reconfigurable Technol. Syst., 2024)

Energy-efficient instruction compression with programmable dictionaries. - Joonas Multanen; Barry de Bruin; Henk Corporaal; Pekka Jääskeläinen (Des. Autom. Embed. Syst., 2024)

Bitstream Database-Driven FPGA Programming Flow Based on Standard OpenCL. - Topi Leppänen; Leevi Leppänen; Joonas Multanen; Pekka Jääskeläinen (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Open Software Stack for Compression-Aware Adaptive Edge Offloading. - Jakub Zádník; Robin Bijl; Jan Solanti; Erno Joensuu; Markku J. Mäkitalo; Pekka Jääskeläinen (WCNC, 2025)

CV-Cast: Computer Vision-Oriented Linear Coding and Transmission. - Jakub Zádník; Michel Kieffer; Anthony Trioux; Markku J. Mäkitalo; Pekka Jääskeläinen (IEEE Trans. Mob. Comput., 2025)

Correction to "CV-Cast: Computer Vision-Oriented Linear Coding and Transmission". - Jakub Zádník; Michel Kieffer; Anthony Trioux; Markku J. Mäkitalo; Pekka Jääskeläinen (IEEE Trans. Mob. Comput., 2025)