A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS. - Pang-Ning Chen; Pen-Jui Peng; Chiro Kao; Yu-Lun Chen; Jri Lee (ISSCC, 2013)

A 94GHz duobinary keying wireless transceiver in 65nm CMOS. - Yu-Lun Chen; Chiro Kao; Pen-Jui Peng; Jri Lee (VLSIC, 2014)

CW/FMCW/pulse radar engines for 24/26GHz multi-standard applications in 65nm CMOS. - Li-Yang Chen; Pen-Jui Peng; Chiro Kao; Yu-Lun Chen; Jri Lee (A-SSCC, 2015)

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies. - Jri Lee; Ping-Chuan Chiang; Pen-Jui Peng; Li-Yang Chen; Chih-Chi Weng (IEEE J. Solid State Circuits, 2015)

A 94 GHz 3D Image Radar Engine With 4TX/4RX Beamforming Scan Technique in 65 nm CMOS Technology. - Pen-Jui Peng; Pang-Ning Chen; Chiro Kao; Yu-Lun Chen; Jri Lee (IEEE J. Solid State Circuits, 2015)

6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOS. - Pen-Jui Peng; Jeng-Feng Li; Li-Yang Chen; Jri Lee (ISSCC, 2017)

A 50-Gb/s Quarter-Rate Voltage-Mode Transmitter with Three-Tap FFE in 40-nm CMOS. - Pen-Jui Peng; Yan-Ting Chen; Chao-Hsuan Chen; Sheng-Tsung Lai; Hsiang-En Huang; Ho-Hsuan Lu; Tsai-Chin Yu (ESSCIRC, 2018)

A 112Gb/s PAM-4 Voltage-Mode Transmitter with 4-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40nm CMOS. - Pen-Jui Peng; Yan-Ting Chen; Sheng-Tsung Lai; Chao-Hsuan Chen; Hsiang-En Huang; Ted Shih (ISSCC, 2019)

6.8 A 100Gb/s NRZ Transmitter with 8-Tap FFE Using a 7b DAC in 40nm CMOS. - Pen-Jui Peng; Sheng-Tsung Lai; Wei-Hung Wang; Chiang-Wei Lin; Wei-Chien Huang; Ted Shih (ISSCC, 2020)

A 56-Gb/s PAM-4 Optical Transceiver with Nonlinear FFE for VCSEL Driver in 40nm CMOS. - Pen-Jui Peng; Hsiang-En Huang; Wei-Chien Huang; Po-Lin Lee; Ming-Wei Lin; Ying-Zong Juang; Sheng-Hsiang Tseng (A-SSCC, 2021)

A 112-Gb/s PAM-4 Voltage-Mode Transmitter With Four-Tap Two-Step FFE and Automatic Phase Alignment Techniques in 40-nm CMOS. - Pen-Jui Peng; Yan-Ting Chen; Sheng-Tsung Lai; Hsiang-En Huang (IEEE J. Solid State Circuits, 2021)

Design of ultra-high-speed Transmitters Beyond 100Gb/s in CMOS Technology. - Pen-Jui Peng (VLSI-DAT, 2022)

A 56-Gb/s PAM-4 Transmitter/Receiver Chipset With Nonlinear FFE for VCSEL-Based Optical Links in 40-nm CMOS. - Pen-Jui Peng; Po-Lin Lee; Hsiang-En Huang; Wei-Jian Huang; Ming-Wei Lin; Ying-Zong Juang; Sheng-Hsiang Tseng (IEEE J. Solid State Circuits, 2022)

A 12-14.5-GHz 10.2-mW -249-dB FoM Fractional-N Subsampling PLL With a High-Linearity Phase Interpolator in 40-nm CMOS. - Yan-Ting Chen; Pen-Jui Peng; Hung-Wen Lin (IEEE Trans. Very Large Scale Integr. Syst., 2022)

A 39-Gb/s PAM-3 Transmitter and ADC-Based Receiver Chipset in CMOS Technologies. - Yen-Po Lin; Chun-Chang Lu; Mei-Hsuan Lu; Yueh-Cheng Tsai; Ping-Hsuan Hsieh; Pen-Jui Peng (A-SSCC, 2024)

7.7 A 2.16pJ/b 112Gb/s PAM-4 Transceiver with Time-Interleaved 2b/3b ADCs and Unbalanced Baud-Rate CDR for XSR Applications in 28nm CMOS. - Yen-Po Lin; Pen-Jui Peng; Chun-Chang Lu; Po-Ting Shen; Yun-Cheng Jao; Ping-Hsuan Hsieh (ISSCC, 2024)

7.6 A 2.06pJ/b 106.25Gb/s PAM-4 Receiver with 3-Tap FFE and 1-Tap Speculative DFE in 28nm CMOS. - Yen-Po Lin; Yun-Cheng Jao; Wu-Hung Hsieh; Pen-Jui Peng (ISSCC, 2025)