Peng Cao
Orcid: 0000-0003-2039-9031Affiliations:
- Southeast University, National ASIC System Engineering Research Center, Nanjing, China
According to our database1,
Peng Cao
authored at least 56 papers
between 2007 and 2024.
Collaborative distances:
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Bibliography
2024
Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS.
Integr., January, 2024
2023
Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM.
IEEE Trans. Very Large Scale Integr. Syst., September, 2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., July, 2023
A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., April, 2023
IEEE Des. Test, February, 2023
Sci. China Inf. Sci., February, 2023
2022
A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model.
CoRR, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022
2021
Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021
2020
Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020
2019
An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation.
IEEE Access, 2019
Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
Proceedings of the International Conference on Computer-Aided Design, 2019
A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
2017
Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach.
IEICE Electron. Express, 2017
IEICE Electron. Express, 2017
2016
An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers.
IEICE Electron. Express, 2016
2015
Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding".
IEEE Trans. Multim., 2015
An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding.
IEEE Trans. Multim., 2015
Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array.
J. Circuits Syst. Comput., 2015
IEICE Trans. Commun., 2015
2014
On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time.
IEEE Trans. Very Large Scale Integr. Syst., 2014
IEICE Electron. Express, 2014
Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor.
Sci. China Inf. Sci., 2014
Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
A Configuration Compression Approach for Coarse-Grain Reconfigurable Architecture for Radar Signal Processing.
Proceedings of the 2014 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2014
2013
Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor.
IEEE Trans. Signal Process., 2013
Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware.
IEEE Trans. Instrum. Meas., 2013
The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip.
IEICE Trans. Inf. Syst., 2013
Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC.
IEICE Trans. Inf. Syst., 2013
IEICE Electron. Express, 2013
Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture.
Sci. China Inf. Sci., 2013
Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
Proceedings of the 2nd IAPR Asian Conference on Pattern Recognition, 2013
2012
Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications.
IEICE Trans. Inf. Syst., 2012
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012
Hybrid-Priority Configuration Cache Supervision Method for Coarse Grained Reconfigurable Architecture.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
A New Approach to Implement Discrete Wavelet Transform on Coarse-Grained Reconfigurable Architecture.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
2010
Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme.
J. Signal Process. Syst., 2010
2009
Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009
2007
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007