An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform. - Chao Wang 068; Wu Zhilin; Peng Cao 002; Li Jie (ICME, 2007)

Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer. - Peng Cao 002; Chao Wang 068; Jun Yang 006; Longxing Shi (ICME, 2009)

Memory-Efficient and High-Performance Two-Dimensional Discrete Wavelet Transform Architecture Based on Decomposed Lifting Algorithm. - Peng Cao 002; Chao Wang 068; Longxing Shi (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009)

Memory-Efficient and High-Speed VLSI Implementation of Two-Dimensional Discrete Wavelet Transform Using Decomposed Lifting Scheme. - Peng Cao 002; Chao Wang 068; Longxing Shi (J. Signal Process. Syst., 2010)

Configuration Cache Management for Coarse-Grained Reconfigurable Architecture with Multi-Array. - Peng Cao 002; Yong Cai; Bo Liu 019; Weiwei Shan (CyberC, 2012)

Memory Bandwidth Optimization Strategy of Coarse-Grained Reconfigurable Architecture. - Peng Cao 002; Huiyan Jiang; Bo Liu 019; Weiwei Shan (CyberC, 2012)

A New Approach to Implement Discrete Wavelet Transform on Coarse-Grained Reconfigurable Architecture. - Jie Li; Xinxiang Ke; Peng Cao 002; Weiwei Shan (CyberC, 2012)

Hybrid-Priority Configuration Cache Supervision Method for Coarse Grained Reconfigurable Architecture. - Bo Liu 019; Peng Cao 002; Jinjiang Yang (CyberC, 2012)

Exploration of Full HD Media Decoding on SDR Baseband Processor. - Chen Mei; Min Li 001; Peng Cao 002; Amir Amin; Chunshu Li; Sofie Pollin; Jun Yang 006 (SiPS, 2012)

Reconfiguration Process Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. - Bo Liu 019; Peng Cao 002; Min Zhu 001; Jun Yang 006; Leibo Liu; Shaojun Wei; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

Date Flow Optimization of Dynamically Coarse Grain Reconfigurable Architecture for Multimedia Applications. - Xinning Liu; Chen Mei; Peng Cao 002; Min Zhu 001; Longxing Shi (IEICE Trans. Inf. Syst., 2012)

A Robust and Efficient Minutia-Based Fingerprint Matching Algorithm. - Wen Wen; Zhi Qi; Zhi Li; Junhao Zhang; Yu Gong; Peng Cao 002 (ACPR, 2013)

An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications. - Leibo Liu; Chenchen Deng; Dong Wang 040; Min Zhu 001; Shouyi Yin; Peng Cao 002; Shaojun Wei (CICC, 2013)

Implementation of multi-standard video decoding algorithms on a coarse-grained reconfigurable multimedia processor. - Leibo Liu; Yingjie Victor Chen; Shouyi Yin; Dong Wang 040; Xing Wang; Shaojun Wei; Li Zhou 015; Hao Lei; Peng Cao 002 (ISCAS, 2013)

Hierarchical representation of on-chip context to reduce reconfiguration time and implementation area for coarse-grained reconfigurable architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (Sci. China Inf. Sci., 2013)

An improved timing monitor for deep dynamic voltage scaling system. - Weiwei Shan; Haolin Gu; Bo Li 033; Xiaoqing Wu; Haikun Jin; Yintao Guo; Peng Cao 002 (IEICE Electron. Express, 2013)

Parallelism Analysis of H.264 Decoder and Realization on a Coarse-Grained Reconfigurable SoC. - Gugang Gao; Peng Cao 002; Jun Yang 006; Longxing Shi (IEICE Trans. Inf. Syst., 2013)

Hardware Software Co-design of H.264 Baseline Encoder on Coarse-Grained Dynamically Reconfigurable Computing System-on-Chip. - Hung K. Nguyen; Peng Cao 002; Xuexiang Wang; Jun Yang 006; Longxing Shi; Min Zhu 001; Leibo Liu; Shaojun Wei (IEICE Trans. Inf. Syst., 2013)

The Organization of On-Chip Data Memory in One Coarse-Grained Reconfigurable Architecture. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013)

Evaluation of Correlation Power Analysis Resistance and Its Application on Asymmetric Mask Protected Data Encryption Standard Hardware. - Weiwei Shan; Xin Chen 039; Bo Li 033; Peng Cao 002; Jie Li; Gugang Gao; Longxing Shi (IEEE Trans. Instrum. Meas., 2013)

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor. - Chen Mei; Min Li 001; Peng Cao 002; Amir Amin; Chunshu Li; Jun Yang 006; Antoine Dejonghe; Liesbet Van der Perre; Longxing Shi; Sofie Pollin (IEEE Trans. Signal Process., 2013)

A Configuration Compression Approach for Coarse-Grain Reconfigurable Architecture for Radar Signal Processing. - Bo Liu 019; Wan-Yu Zhu; Yang Liu; Peng Cao 002 (CyberC, 2014)

Configuration approaches to improve computing efficiency of coarse-grained reconfigurable multimedia processor. - Chen Yang 005; Leibo Liu; Yansheng Wang; Shouyi Yin; Peng Cao 002; Shaojun Wei (FPL, 2014)

Hierarchical Pipeline Optimization of Coarse Grained Reconfigurable Processor for Multimedia Applications. - Chen Mei; Peng Cao 002; Yang Zhang 132; Bo Liu 019; Leibo Liu (IPDPS Workshops, 2014)

Implementation of multi-standard video decoder on a heterogeneous coarse-grained reconfigurable processor. - Leibo Liu; Yingjie Victor Chen; Dong Wang 040; Shouyi Yin; Xing Wang; Long Wang; Hao Lei; Peng Cao 002; Shaojun Wei (Sci. China Inf. Sci., 2014)

VLSI design of a reconfigurable S-box based on memory sharing method. - Weiwei Shan; Xiao Zhang; Xingyuan Fu; Peng Cao 002 (IEICE Electron. Express, 2014)

A parallel arithmetic array for accelerating compute-intensive applications. - Dong Wang 040; Peng Cao 002; Yang Xiao 004 (IEICE Electron. Express, 2014)

Reduced-error constant correction truncated multiplier. - Dong Wang 040; Peng Cao 002; Yang Xiao 004 (IEICE Electron. Express, 2014)

On-Chip Memory Hierarchy in One Coarse-Grained Reconfigurable Architecture to Compress Memory Space and to Reduce Reconfiguration Time and Data-Reference Time. - Yansheng Wang; Leibo Liu; Shouyi Yin; Min Zhu 001; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Very Large Scale Integr. Syst., 2014)

A GPS Bit Synchronization Method Based on Frequency Compensation. - Xinning Liu; Yuxiang Niu; Jun Yang 006; Peng Cao 002 (IEICE Trans. Commun., 2015)

Configuration Approaches to Enhance Computing Efficiency of Coarse-Grained Reconfigurable Array. - Chen Yang 005; Leibo Liu; Yansheng Wang; Shouyi Yin; Peng Cao 002; Shaojun Wei (J. Circuits Syst. Comput., 2015)

An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding. - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

Correction to "An Energy-Efficient Coarse-Grained Reconfigurable Processing Unit for Multiple-Standard Video Decoding". - Leibo Liu; Dong Wang 040; Min Zhu 001; Yansheng Wang; Shouyi Yin; Peng Cao 002; Jun Yang 006; Shaojun Wei (IEEE Trans. Multim., 2015)

Timing monitoring paths selection for wide voltage IC. - Weiwei Shan; Wentao Dai; Youhua Shi; Peng Cao 002; Xiaoyan Xiang (IEICE Electron. Express, 2016)

An area-efficient design of reconfigurable S-box for parallel implementation of block ciphers. - Jinjiang Yang; Ge Wei; Peng Cao 002; Jun Yang 006 (IEICE Electron. Express, 2016)

Efficient AES cipher on coarse-grained reconfigurable architecture. - Chao Wang 068; Peng Cao 002; Jun Yang 006 (IEICE Electron. Express, 2017)

Coarse-grained reconfigurable architecture with hierarchical context cache structure and management approach. - Chao Wang 068; Peng Cao 002; Bo Liu 019; Jun Yang 006 (IEICE Electron. Express, 2017)

Context Management Scheme Optimization of Coarse-Grained Reconfigurable Architecture for Multimedia Applications. - Peng Cao 002; Bo Liu 019; Jinjiang Yang; Jun Yang 006; Meng Zhang; Longxing Shi (IEEE Trans. Very Large Scale Integr. Syst., 2017)

A Statistical Current and Delay Model Based on Log-Skew-Normal Distribution for Low Voltage Region. - Peng Cao 002; Jiangping Wu; Zhiyuan Liu 011; Jingjing Guo; Jun Yang 006; Longxing Shi (ACM Great Lakes Symposium on VLSI, 2019)

A Statistical Timing Model for Low Voltage Design Considering Process Variation. - Peng Cao 002; Zhiyuan Liu 011; Jiangping Wu; Jingjing Guo; Jun Yang 006; Longxing Shi (ICCAD, 2019)

A Statistical Timing Model for CMOS Inverter in Near-threshold Region Considering Input Transition Time. - Peng Cao 002; Zhiyuan Liu 011; Bingqian Xu; Jingjing Guo (ICECS, 2019)

Accurate and Efficient Interdependent Timing Model for Flip-Flop in Wide Voltage Region. - Peng Cao 002; Zhiyuan Liu 011; Jingjing Guo; Haoyu Pang; Jiangping Wu; Jun Yang 006 (NEWCAS, 2019)

An Analytical Gate Delay Model in Near/Subthreshold Domain Considering Process Variation. - Peng Cao 002; Zhiyuan Liu 011; Jingjing Guo; Jiangping Wu (IEEE Access, 2019)

A Learning-Based Timing Prediction Framework for Wide Supply Voltage Design. - Wei Bao; Peng Cao 002; Hao Cai 001; Aiguo Bu (ACM Great Lakes Symposium on VLSI, 2020)

Statistical Timing Model for Subthreshold Circuit with Correlated Variation Consideration. - Jingjing Guo; Peng Cao 002; Mengxiao Li; Zhiyuan Liu 011; Jun Yang 006 (ISCAS, 2020)

A Timing Prediction Framework for Wide Voltage Design with Data Augmentation Strategy. - Peng Cao 002; Wei Bao; Kai Wang; Tai Yang (ASP-DAC, 2021)

An Adaptive Delay Model for Timing Yield Estimation under Wide-Voltage Range. - Hao Yan 002; Xiao Shi 001; Chengzhen Xuan; Peng Cao 002; Longxing Shi (ASP-DAC, 2021)

Analytical Delay Model in Near-Threshold Domain Considering Transition Time. - Haiyang Jiang 014; Bingqian Xu; Peng Cao 002; Hao Cai 001 (ICTA, 2021)

Semi-Analytical Path Delay Variation Model With Adjacent Gates Decorrelation for Subthreshold Circuits. - Jingjing Guo; Peng Cao 002; Mengxiao Li; Yu Gong; Zhiyuan Liu 011; Geng Bai; Jun Yang 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

A Graph Neural Network Method for Fast ECO Leakage Power Optimization. - Kai Wang; Peng Cao 002 (ASP-DAC, 2022)

Pre-Routing Path Delay Estimation Based on Transformer and Residual Framework. - Tai Yang; Guoqing He; Peng Cao 002 (ASP-DAC, 2022)

A Timing Yield Model for SRAM Cells in Sub/Near-threshold Voltages Based on A Compact Drain Current Model. - Shan Shen; Peng Cao 002; Ming Ling; Longxing Shi (CoRR, 2022)

An efficient path delay variability model for wide-voltage-range digital circuits. - Weiwei Shan; Yuqiang Cui; Wentao Dai; Xinning Liu; Jingjing Guo; Peng Cao 002; Jun Yang 006 (Sci. China Inf. Sci., 2023)

Topology-Aided Multicorner Timing Predictor for Wide Voltage Design. - Peng Cao 002; Tai Yang; Kai Wang; Wei Bao; Hao Yan 002 (IEEE Des. Test, 2023)

A Timing Yield Model for SRAM Cells at Sub/Near-Threshold Voltages Based on a Compact Drain Current Model. - Shan Shen; Peng Cao 002; Ming Ling; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

TF-Predictor: Transformer-Based Prerouting Path Delay Prediction Framework. - Peng Cao 002; Guoqing He; Tai Yang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Efficient and Accurate ECO Leakage Optimization Framework With GNN and Bidirectional LSTM. - Peng Cao 002; Guoqing He; Wenjie Ding; Zhanhua Zhang; Kai Wang; Jun Yang 006 (IEEE Trans. Very Large Scale Integr. Syst., 2023)

Heterogeneous Graph Attention Network Based Statistical Timing Library Characterization with Parasitic RC Reduction. - Xu Cheng; Yuyang Ye 001; Guoqing He; Qianqian Song; Peng Cao 002 (ASPDAC, 2024)

An Optimization-aware Pre-Routing Timing Prediction Framework Based on Heterogeneous Graph Learning. - Guoqing He; Wenjie Ding; Yuyang Ye 001; Xu Cheng; Qianqian Song; Peng Cao 002 (ASPDAC, 2024)

A Physical and Timing Aware Placement Optimization Framework Based on Graph Neural Network. - Wenjie Ding; Zhanhua Zhang; Guoqing He; Peng Cao 002 (ICCAD, 2024)

LAG-Sizer: A Novel Gate Sizer Based on Leak Generative Adversarial Network with Feature Fusion. - Zhanhua Zhang; Wenjie Ding; Guoqing He; Peng Cao 002 (ICCAD, 2024)

Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning. - Tao Bai; Zeyuan Deng; Peng Cao 002 (MLCAD, 2024)

Ultra-low-power one-hot transmission-gate multiplexer (OTG-MUX) scalable into large fan-in circuits in 28 nm CMOS. - Yuqiang Cui; Weiwei Shan; Peng Cao 002 (Integr., 2024)

Cell Library Characterization for Composite Current Source Models Based on Gaussian Process Regression and Active Learning. - Tao Bai; Junzhuo Zhou; Zeyuan Deng; Ting-Jung Lin; Wei W. Xing; Peng Cao 002; Lei He 001 (CoRR, 2025)

An On-Chip-Training Keyword-Spotting Chip Using Interleaved Pipeline and Computation-in-Memory Cluster in 28-nm CMOS. - Junyi Qian; Cai Li; Long Chen; Ruidong Li; Tuo Li; Peng Cao 002; Xin Si; Weiwei Shan (IEEE Trans. Very Large Scale Integr. Syst., 2025)