Peng Liu

Orcid: 0000-0001-9107-6673

Affiliations:
  • Zhejiang University, Department of Information Science and Electronic Engineering, Hangzhou, China


According to our database1, Peng Liu authored at least 57 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

Online presence:

On csauthors.net:

Bibliography

2023
RUPA: A High Performance, Energy Efficient Accelerator for Rule-Based Password Generation in Heterogenous Password Recovery System.
IEEE Trans. Computers, April, 2023

Adaptive Caching Policies for Chiplet Systems Based on Reinforcement Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
On a Consistency Testing Model and Strategy for Revealing RISC Processor's Dark Instructions and Vulnerabilities.
IEEE Trans. Computers, 2022

IMSC: Instruction set architecture monitor and secure cache for protecting processor systems from undocumented instructions.
IET Inf. Secur., 2022

High-Performance Password Recovery Hardware Going From GPU to Hybrid CPU-FPGA Platform.
IEEE Consumer Electron. Mag., 2022

2021
A Deep Learning-Based FPGA Function Block Detection Method With Bitstream to Image Transformation.
IEEE Access, 2021

Hardware Trojan Detection Method for Inspecting Integrated Circuits Based on Machine Learning.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2019
An Energy-Efficient Accelerator Based on Hybrid CPU-FPGA Devices for Password Recovery.
IEEE Trans. Computers, 2019

Ensemble-Learning-Based Hardware Trojans Detection Method by Detecting the Trigger Nets.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Hardware Trojans Detection at Register Transfer Level Based on Machine Learning.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Energy-Efficient RAR3 Password Recovery with Dual-Granularity Data Path Strategy.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Hadoop Configuration Tuning With Ensemble Modeling and Metaheuristic Optimization.
IEEE Access, 2018

2017
An Adaptive PAM-4 Analog Equalizer With Boosting-State Detection in the Time Domain.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Adaptive Coherence Granularity for Multi-Socket Systems.
IEEE Trans. Computers, 2017

2016
Building Expressive and Area-Efficient Directories with Hybrid Representation and Adaptive Multi-Granular Tracking.
IEEE Trans. Computers, 2016

Thread-Aware Adaptive Prefetcher on Multicore Systems: Improving the Performance for Multithreaded Workloads.
ACM Trans. Archit. Code Optim., 2016

Heterogeneous 3-D circuits: Integrating free-space optics with CMOS.
Microelectron. J., 2016

PSS4: Four-Phase Shifted Sinusoid Symbol Signaling for High Speed I/O interconnects.
Comput. Electr. Eng., 2016

Threads and Data Mapping: Affinity Analysis for Traffic Reduction.
IEEE Comput. Archit. Lett., 2016

H-TDMS: A System for Traffic Big Data Management.
Proceedings of the Advanced Computer Architecture - 11th Conference, 2016

2015
Physical-based modeling and fast simulation of wireline links.
Proceedings of the 2015 IFIP/IEEE International Conference on Very Large Scale Integration, 2015

A PAM-4 adaptive analog equalizer with decoupling control loops for 25-Gb/s CMOS serial-link receiver.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Exploiting multi-band transmission line interconnects to improve the efficiency of cache coherence in multiprocessor system-on-chip.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

A 20 GHz high speed, low jitter, high accuracy and wide correction range duty cycle corrector.
Proceedings of the 28th IEEE International System-on-Chip Conference, 2015

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

2014
On self-tuning networks-on-chip for dynamic network-flow dominance adaptation.
ACM Trans. Embed. Comput. Syst., 2014

DEAM: Decoupled, Expressive, Area-Efficient Metadata Cache.
J. Comput. Sci. Technol., 2014

A new fault injection method for evaluation of combining SEU and SET effects on circuit reliability.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A novel signaling technique for high-speed wireline backplane transceiver: Four phase-shifted sinusoid symbol (PSS-4).
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A Thread-Aware Adaptive Data Prefetcher.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

2013
An efficient protocol with synchronization accelerator for multi-processor embedded systems.
Parallel Comput., 2013

Avoiding request-request type message-dependent deadlocks in networks-on-chips.
Parallel Comput., 2013

Efficient multicast schemes for 3-D Networks-on-Chip.
J. Syst. Archit., 2013

Energy Efficient Run-Time Incremental Mapping for 3-D Networks-on-Chip.
J. Comput. Sci. Technol., 2013

Scalable-Grain Pipeline Parallelization Method for Multi-core Systems.
Proceedings of the Network and Parallel Computing - 10th IFIP International Conference, 2013

A novel energy-efficient serializer design method for gigascale systems.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Building expressive, area-efficient coherence directories.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013

2012
Using Transmission Lines for Global On-Chip Communication.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

An efficient scheduler of RTOS for multi/many-core system.
Comput. Electr. Eng., 2012

2011
On an efficient NoC multicasting scheme in support of multiple applications running on irregular sub-networks.
Microprocess. Microsystems, 2011

A networks-on-chip emulation/verification framework.
Int. J. High Perform. Syst. Archit., 2011

Low latency and energy efficient multicasting schemes for 3D NoC-based SoCs.
Proceedings of the IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 2011

Power-Aware Run-Time Incremental Mapping for 3-D Networks-on-Chip.
Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011

An Efficient Architectural Design of Hardware Interface for Heterogeneous Multi-core System.
Proceedings of the Network and Parallel Computing - 8th IFIP International Conference, 2011

A design space exploration of transmission-line links for on-chip interconnect.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

2010
A power-aware mapping approach to map IP cores onto NoCs under bandwidth and latency constraints.
ACM Trans. Archit. Code Optim., 2010

Network interface design based on mutual interface definition.
Int. J. High Perform. Syst. Archit., 2010

A synergetic operating unit on NoC layer for CMP system.
Int. J. High Perform. Syst. Archit., 2010

Efficient multicasting scheme for irregular mesh-based NoCs.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

An intra-chip free-space optical interconnect.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

2009
A networks-on-chip architecture design space exploration - The LIB.
Comput. Electr. Eng., 2009

A NoC Emulation/Verification Framework.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

2005
A processor for MPEG decoder SOC: a software/hardware co-design approach.
Proceedings of the Electronic Imaging: Image and Video Communications and Processing 2005, 2005

2004
Embedded software optimization for MP3 decoder implemented on RISC core.
IEEE Trans. Consumer Electron., 2004

2002
Hardware/software codesign for HDTV source decoder on system level.
Proceedings of the Visual Communications and Image Processing 2002, 2002

A bus arbitration scheme for HDTV decoder SoC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2002, 2002

2001
SPMD architecture for DSP-based data encryption communication system.
Proceedings of the Security and Watermarking of Multimedia Contents III, 2001


  Loading...