A scan disabling-based BAST scheme for test cost reduction. - Zhiqiang You; Weizheng Wang 002; Zhiping Dou; Peng Liu 045; Jishun Kuang (IEICE Electron. Express, 2011)

Integrated Heuristic for Hardware/Software Co-design on Reconfigurable Devices. - Peng Liu 045; Jigang Wu; Yongji Wang 002 (PDCAT, 2012)

Switching activity reduction for scan-based BIST using weighted scan input data. - Weizheng Wang 002; Jishun Kuang; Peng Liu 045; Xin Peng; Zhiqiang You (IEICE Electron. Express, 2012)

A scan disabling-based BAST scheme for test cost and test power reduction. - Zhiqiang You; Weizheng Wang 002; Peng Liu 045; Jishun Kuang; Zheng Qin (IEICE Electron. Express, 2012)

Low power logic BIST with high test effectiveness. - Weizheng Wang 002; Peng Liu 045; Shuo Cai; Lingyun Xiang (IEICE Electron. Express, 2013)

Hybrid algorithms for hardware/software partitioning and scheduling on reconfigurable devices. - Peng Liu 045; Jigang Wu; Yongji Wang 002 (Math. Comput. Model., 2013)

Logic operation-based DFT method and 1R memristive crossbar March-like test algorithm. - Peng Liu 045; Zhiqiang You; Jishun Kuang; Zhipeng Hu; Weizheng Wang 002 (IEICE Electron. Express, 2015)

A parallel-SSHI rectifier for ultra-low-voltage piezoelectric vibration energy harvesting. - Liao Wu; Jishun Kuang; Zhiqiang You; Peng Liu 045; Shuo Cai (IEICE Electron. Express, 2016)

Reliability evaluation of logic circuits based on transient faults propagation metrics. - Shuo Cai; Fei Yu 009; Weizheng Wang 002; Tieqiao Liu; Peng Liu 045; Wei Wang 229 (IEICE Electron. Express, 2017)

A novel test data compression approach based on bit reversion. - Shuo Cai; Yinbo Zhou; Peng Liu 045; Fei Yu 009; Wei Wang 229 (IEICE Electron. Express, 2017)

A direct AC-DC converter integrated with SSHI circuit for piezoelectric energy harvesting. - Liao Wu; Chenrui Guo; Peng Liu 045; Wei Wang 229 (IEICE Electron. Express, 2017)

A Novel Linguistic Steganography Based on Synonym Run-Length Encoding. - Lingyun Xiang; Xinhui Wang; Chunfang Yang; Peng Liu 045 (IEICE Trans. Inf. Syst., 2017)

Defect Analysis and Parallel March Test Algorithm for 3D Hybrid CMOS-Memristor Memory. - Peng Liu 045; Jigang Wu; Zhiqiang You; Michael Elimu; Weizheng Wang 002; Shuo Cai (ATS, 2018)

An efficient controlled LFSR hybrid BIST scheme. - Tieqiao Liu; Peng Liu 045; Yi Liu (IEICE Electron. Express, 2018)

A Secure DFT Architecture Protecting Crypto Chips Against Scan-Based Attacks. - Weizheng Wang 002; Jincheng Wang; Wei Wang 229; Peng Liu 045; Shuo Cai (IEEE Access, 2019)

Jointly Learning Multiple Curvature Descriptor for 3D Palmprint Recognition. - Lunke Fei; Jianyang Qin; Peng Liu 045; Jie Wen 001; Chunwei Tian; Bob Zhang 001; Shuping Zhao (ICPR, 2020)

Restoring Survivable Spanning Tree: An Alternative Algorithm. - Lulu Zheng; Yalan Wu; Jiale Huang; Peng Liu 045; Jigang Wu (PAAP, 2020)

Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults. - Shuo Cai; Binyong He; Weizheng Wang 002; Peng Liu 045; Fei Yu 009; Lairong Yin; Bo Li 051 (J. Electron. Test., 2020)

F3D: Accelerating 3D Convolutional Neural Networks in Frequency Space Using ReRAM. - Bosheng Liu; Zhuoshen Jiang; Jigang Wu; Xiaoming Chen 003; Yinhe Han 001; Peng Liu 045 (DAC, 2021)

Fault Modeling and Efficient Testing of Memristor-Based Memory. - Peng Liu 045; Zhiqiang You; Jigang Wu; Bosheng Liu; Yinhe Han 001; Krishnendu Chakrabarty (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Integrating Two Logics Into One Crossbar Array for Logic Gate Design. - Lian Yao; Peng Liu 045; Jigang Wu; Yinhe Han 001; Yuehang Zhong; Zhiqiang You (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Defect Analysis and Parallel Testing for 3D Hybrid CMOS-Memristor Memory. - Peng Liu 045; Zhiqiang You; Jigang Wu; Michael Elimu; Weizheng Wang 002; Shuo Cai; Yinhe Han 001 (IEEE Trans. Emerg. Top. Comput., 2021)

Fast algorithms for restoring survivable spanning connection. - Jiale Huang; Lulu Zheng; Yalan Wu; Peng Liu 045; Jigang Wu (Comput. Electr. Eng., 2022)

An improved reconfigurable logic in resistive random access memory. - Yi Zhao; Hui Chen; Peng Liu 045; Jigang Wu; Dongxiang Luo (Integr., 2022)

Reconfiguration algorithms for synchronous communication on switch based degradable arrays. - Yalan Wu; Jigang Wu; Peng Liu 045; Yinhe Han 001; Thambipillai Srikanthan (Parallel Comput., 2022)

Search-Free Inference Acceleration for Sparse Convolutional Neural Networks. - Bosheng Liu; Xiaoming Chen 003; Yinhe Han 001; Jigang Wu; Liang Chang 003; Peng Liu 045; Haobo Xu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

Ensuring Cryptography Chips Security by Preventing Scan-Based Side-Channel Attacks With Improved DFT Architecture. - Weizheng Wang 002; Xiangqi Wang; Jin Wang 001; Neal N. Xiong; Shuo Cai; Peng Liu 045 (IEEE Trans. Syst. Man Cybern. Syst., 2022)

Accurate Reliability Boundary Evaluation of Approximate Arithmetic Circuit. - Zhen Wang 042; Guofa Zhang; Peng Liu 045; Jing Ye 001; Jianhui Jiang (IEEE Trans. Very Large Scale Integr. Syst., 2022)

Accelerating Convolutional Neural Networks in Frequency Domain via Kernel-Sharing Approach. - Bosheng Liu; Hongyi Liang; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Yinhe Han 001 (ASP-DAC, 2023)

Double-Layered Dual-Syndrome Trellis Codes Utilizing Channel Knowledge for Robust Steganography. - Qingxiao Guan; Peng Liu 045; Weiming Zhang 001; Wei Lu 001; Xinpeng Zhang 001 (IEEE Trans. Inf. Forensics Secur., 2023)

Frequency-Domain Inference Acceleration for Convolutional Neural Networks Using ReRAMs. - Bosheng Liu; Zhuoshen Jiang; Yalan Wu; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Qingguo Zhou; Yinhe Han 001 (IEEE Trans. Parallel Distributed Syst., 2023)

Accelerating Frequency-domain Convolutional Neural Networks Inference using FPGAs. - Yi Chen; Bosheng Liu; Yongqi Xu; Jigang Wu; Xiaoming Chen 003; Peng Liu 045; Qingguo Zhou; Yinhe Han 001 (ISCAS, 2024)

A Complementary Resistive Switch-Based Balanced Ternary Logic. - Zhijian Peng; Peng Liu 045; Lian Yao; Zhiqiang You; Bosheng Liu; Yang Yi; Jigang Wu (ITC-Asia, 2024)

BitQ: Tailoring Block Floating Point Precision for Improved DNN Efficiency on Resource-Constrained Devices. - Yongqi Xu; Yujian Lee; Gao Yi; Bosheng Liu; Yucong Chen; Peng Liu 045; Jigang Wu; Xiaoming Chen 003; Yinhe Han 001 (CoRR, 2024)

DAF: An Effective Design-for-Testability Authorization Framework Based on Obfuscation Mechanisms for Defending Complex Attacks. - Weizheng Wang 002; Xingxing Gong; Xiangqi Wang; Shuo Cai; Peng Liu 045; Neal N. Xiong (IEEE Internet Things J., 2024)

SSA: An Effective Secure Scan Architecture Based on Hidden, Randomly Inserted Keys and PUF. - Weizheng Wang 002; Zhizhi Wu; Jinhai Chen; Peng Liu 045; Shuo Cai; Neal N. Xiong (IEEE Internet Things J., 2025)