Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks. - Peng Xu 052; Lin Zhang; Xuanzhou Liu; Jiaqi Sun; Yue Zhao 016; Haiqin Yang; Bei Yu 001 (ICML, 2023)

Do Not Train It: A Linear Neural Architecture Search of Graph Neural Networks. - Peng Xu 052; Lin Zhang; Xuanzhou Liu; Jiaqi Sun; Yue Zhao 016; Haiqing Yang; Bei Yu 001 (CoRR, 2023)

p-Laplacian Adaptation for Generative Pre-trained Vision-Language Models. - Haoyuan Wu; Xinyun Zhang; Peng Xu 052; Peiyu Liao; Xufeng Yao; Bei Yu 001 (AAAI, 2024)

Performance-Driven Analog Layout Automation: Current Status and Future Directions (Invited Paper). - Peng Xu 052; Jintao Li; Tsung-Yi Ho; Bei Yu 001; Keren Zhu 001 (ASPDAC, 2024)

Efficient Bilevel Source Mask Optimization. - Guojin Chen; Hongquan He; Peng Xu 052; Hao Geng; Bei Yu 001 (DAC, 2024)

NeuroSelect: Learning to Select Clauses in SAT Solvers. - Hongduo Liu; Peng Xu 052; Yuan Pu 001; Lihao Yin; Hui-Ling Zhen; Mingxuan Yuan; Tsung-Yi Ho; Bei Yu 001 (DAC, 2024)

Performance-driven Analog Routing via Heterogeneous 3DGNN and Potential Relaxation. - Peng Xu 052; Guojin Chen; Keren Zhu 001; Tinghuan Chen; Tsung-Yi Ho; Bei Yu 001 (DAC, 2024)

Disentangle, Align and Generalize: Learning A Timing Predictor from Different Technology Nodes. - Xinyun Zhang; Binwu Zhu; Fangzhou Liu; Ziyi Wang 010; Peng Xu 052; Hong Xu 001; Bei Yu 001 (DAC, 2024)

RankTuner: When Design Tool Parameter Tuning Meets Preference Bayesian Optimization. - Peng Xu 052; Su Zheng; Yuyang Ye 001; Chen Bai; Siyuan Xu; Hao Geng; Tsung-Yi Ho; Bei Yu 001 (ICCAD, 2024)

DeepOTF: Learning Equations-constrained Prediction for Electromagnetic Behavior. - Peng Xu 052; Siyuan Xu; Tinghuan Chen; Guojin Chen; Tsung-Yi Ho; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2024)

LLMShare: Optimizing LLM Inference Serving with Hardware Architecture Exploration. - Hongduo Liu; Chen Bai; Peng Xu 052; Lihao Yin; Xianzhi Yu; Hui-Ling Zhen; Mingxuan Yuan; Tsung-Yi Ho; Bei Yu 001 (DAC, 2025)

Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree Search. - Yuyang Ye 001; Xiangfei Hu; Yuchen Liu; Peng Xu 052; Yu Gong 002; Tinghuan Chen; Hao Yan 002; Bei Yu 001; Longxing Shi (DAC, 2025)

Learning-Driven Physically Aware Large-Scale Circuit Gate Sizing. - Yuyang Ye 001; Peng Xu 052; Lizheng Ren; Tinghuan Chen; Hao Yan 002; Bei Yu 001; Longxing Shi (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Prerouting Timing Prediction Across Different Technology Nodes. - Xinyun Zhang; Binwu Zhu; Fangzhou Liu; Jiaxi Jiang; Ziyi Wang 010; Peng Xu 052; Hong Xu 001; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Lay-Net: Grafting Netlist Knowledge on Layout-Based Congestion Prediction. - Lancheng Zou; Su Zheng; Peng Xu 052; Siting Liu 002; Bei Yu 001; Martin D. F. Wong (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

Rank-DSE: Neural Pareto Comparator of Microarchitecture Design Space Exploration. - Peng Xu 052; Su Zheng; Mingzi Wang; Ziyang Yu 001; Shixin Chen; Tinghuan Chen; Keren Zhu 001; Tsung-Yi Ho; Bei Yu 001 (ACM Trans. Design Autom. Electr. Syst., 2025)

SMART: Graph Learning-Boosted Subcircuit Matching for Large-Scale Analog Circuits. - Jindong Tu; Yapeng Li; Pengjia Li; Peng Xu 052; Qianru Zhang; Sanping Wan; Yongsheng Sun; Bei Yu 001; Tinghuan Chen (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)

PARoute2: Enhanced Analog Routing via Performance-Drive Guidance Generation. - Peng Xu 052; Jindong Tu; Guojin Chen; Keren Zhu 001; Tinghuan Chen; Tsung-Yi Ho; Bei Yu 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)