Simulation study of N-hit SET variation in differential cascade voltage switch logical circuits. - Pengcheng Huang 003; Shuming Chen; Jianjun Chen; Zhenyu Wu; Zhengfa Liang; Chunmei Hu; Bin Liang; Biwei Liu (Sci. China Inf. Sci., 2015)

Evaluating the single event sensitivity of dynamic comparator in 5 Gbps SerDes. - Chunmei Hu; Shuming Chen; Pengcheng Huang 003; Yao Liu; Jianjun Chen (IEICE Electron. Express, 2015)

Single event transient propagation in dynamic complementary metal oxide semiconductor cascade circuits. - Jingyan Xu; Shuming Chen; Pengcheng Huang 003; Peipei Hao; Ruiqiang Song; Chunmei Hu (IEICE Electron. Express, 2015)

Single event upset induced by single event double transient and its well-structure dependency in 65-nm bulk CMOS technology. - Pengcheng Huang 003; Shuming Chen; Jianjun Chen (Sci. China Inf. Sci., 2016)

Cost-effective SET-tolerant clock distribution network design by mitigating single event transient propagation. - Peipei Hao; Shuming Chen; Pengcheng Huang 003; Jianjun Chen; Bin Liang (Sci. China Inf. Sci., 2017)

Angular dependency on heavy-ion-induced single-event multiple transients (SEMT) in 65 nm twin-well and triple-well CMOS technology. - Jizuo Zhang; Jianjun Chen; Pengcheng Huang 003; Shouping Li; Liang Fang (Microelectron. Reliab., 2018)

Fast Dynamic IR-Drop Prediction Using Machine Learning in Bulk FinFET Technologies. - Pengcheng Huang 003; Chiyuan Ma; Zhenyu Wu (Symmetry, 2021)

Experimental Investigation of Charge Sharing Induced SET Depending on Transistors in Abutted Rows in 65 nm Bulk CMOS Technology. - Xiaowei He; Daheng Yue; Pengcheng Huang 003; Zhenyu Zhao (IEEE Access, 2022)

CAUTS: Clock Tree Optimization via Skewed Cells With Complementary Asymmetrical Uniform Transistor Sizing. - Pengcheng Huang 003; Yaohua Wang; Zhenyu Zhao; Daheng Yue (IEEE Trans. Very Large Scale Integr. Syst., 2024)