Pengcheng Li

Affiliations:
  • Google Inc., Mountain View, CA, USA
  • University of Rochester, Department of Computer Science, NY, USA


According to our database1, Pengcheng Li authored at least 17 papers between 2013 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2022
Graph Neural Networks Based Memory Inefficiency Detection Using Selective Sampling.
Proceedings of the SC22: International Conference for High Performance Computing, 2022

2021
Uniform lease vs. LRU cache: analysis and evaluation.
Proceedings of the ISMM '21: 2021 ACM SIGPLAN International Symposium on Memory Management, 2021

GRAPHSPY: Fused Program Semantic Embedding through Graph Neural Networks for Memory Efficiency.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2019
Timescale functions for parallel memory allocation.
Proceedings of the 2019 ACM SIGPLAN International Symposium on Memory Management, 2019

Beating OPT with Statistical Clairvoyance and Variable Size Caching.
Proceedings of the Twenty-Fourth International Conference on Architectural Support for Programming Languages and Operating Systems, 2019

2018
Footprint modeling of cache associativity and granularity.
Proceedings of the International Symposium on Memory Systems, 2018

2017
LD: Low-Overhead GPU Race Detection Without Access Monitoring.
ACM Trans. Archit. Code Optim., 2017

Thread Data Sharing in Cache: Theory and Measurement.
Proceedings of the 22nd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2017

Adaptive Software Caching for Efficient NVRAM Data Persistence.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium, 2017

2016
Data-centric combinatorial optimization of parallel code.
Proceedings of the 21st ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2016

Adaptive Software Caching for Efficient NVRAM Data Persistence.
Proceedings of the Languages and Compilers for Parallel Computing, 2016

Rethinking a heap hierarchy as a cache hierarchy: a higher-order theory of memory demand (HOTM).
Proceedings of the 2016 ACM SIGPLAN International Symposium on Memory Management, Santa Barbara, CA, USA, June 14, 2016

Compositional model of coherence and NUMA effects for optimizing thread and data placement.
Proceedings of the 2016 IEEE International Symposium on Performance Analysis of Systems and Software, 2016

2015
Assessing Safe Task Parallelism in SPEC 2006 INT.
Proceedings of the 15th IEEE/ACM International Symposium on Cluster, 2015

2014
Modeling heap data growth using average liveness.
Proceedings of the International Symposium on Memory Management, 2014

Code Layout Optimization for Defensiveness and Politeness in Shared Cache.
Proceedings of the 43rd International Conference on Parallel Processing, 2014

2013
All-window data liveness.
Proceedings of the ACM SIGPLAN Workshop on Memory Systems Performance and Correctness, 2013


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