A high performance microprocessor with DSP extensions optimized for the Virtex-4 FPGA. - Andreas Ehliar; Per Karlström; Dake Liu (FPL, 2008)

High-performance, low-latency field-programmable gate array-based floating-point adder and multiplier units in a Virtex 4. - Per Karlström; Andreas Ehliar; Dake Liu (IET Comput. Digit. Tech., 2008)

NoGAP: A Micro Architecture Construction Framework. - Per Karlström; Dake Liu (SAMOS, 2009)

NoGapCL: A flexible common language for processor hardware description. - Wenbiao Zhou; Per Karlström; Dake Liu (DDECS, 2010)

Implementation of a Floating Point Adder and Subtracter in NoGAP, A Comparative Case Study. - Per Karlström; Wenbiao Zhou; Dake Liu (EUC, 2010)

Operation Classification for Control Path Synthetization with NoGAP. - Per Karlström; Wenbiao Zhou; Dake Liu (ITNG, 2010)

Automatic port and bus sizing in NoGap. - Per Karlström; Wenbiao Zhou; Dake Liu (ICSAMOS, 2010)

Automatic Synthesizable HDL Generator for NoGAP. - Wenbiao Zhou; Per Karlström; Dake Liu (ACIS-ICIS, 2012)

Generator Flow: An XML Configurable Design Pattern Used in NoGAP. - Per Karlström; Wenbiao Zhou (ITNG, 2012)

The Effects of Low Latency on Pointing and Steering Tasks. - Sebastian Friston; Per Karlström; Anthony Steed (IEEE Trans. Vis. Comput. Graph., 2016)