A 965-Mb/s 1.0-μm standard CMOS twin-pipe serial/parallel multiplier. - Per Larsson-Edefors (IEEE J. Solid State Circuits, 1996)

Technology mapping onto very-high-speed standard CMOS hardware. - Per Larsson-Edefors (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996)

A Miniature Serial-Data SIMD Architecture. - Per Larsson-Edefors (EUROMICRO, 1998)

Separation and extraction of short-circuit power consumption in digital CMOS VLSI circuits. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ISLPED, 1998)

A leakage-tolerant multi-phase keeper for wide domino circuits. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ICECS, 1999)

GLMC: interconnect length estimation by growth-limited multifold clustering. - Atila Alvandpour; Per Larsson-Edefors; Christer Svensson (ISCAS, 2000)

An interconnect-driven design of a DFT processor. - Daniel Eckerbert; Henrik Eriksson; Per Larsson-Edefors; Anders Edman (ISCAS, 2000)

Impact of Voltage Scaling on Glitch Power Consumption. - Henrik Eriksson; Per Larsson-Edefors (PATMOS, 2000)

Interconnect-Driven Short-Circuit Power Modeling. - Daniel Eckerbert; Per Larsson-Edefors (DSD, 2001)

VLSI implementation of CRC-32 for 10 Gigabit Ethernet. - Tomas Henriksson; Henrik Eriksson; Ulf Nordqvist; Per Larsson-Edefors; Dake Liu (ICECS, 2001)

Cycle-true leakage current modeling for CMOS gates. - Daniel Eckerbert; Per Larsson-Edefors (ISCAS (5), 2001)

A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. - Henrik Eriksson; Per Larsson-Edefors; Atila Alvandpour (ISCAS (4), 2001)

A regular parallel multiplier which utilizes multiple carry-propagate adders. - Henrik Eriksson; Per Larsson-Edefors; William P. Marnane (ISCAS (4), 2001)

DSP-PP: A Simulator/Estimator of Power Consumption and Performance for Parallel DSP Architectures. - Minh Quang Do; Lars Bengtsson; Per Larsson-Edefors (Applied Informatics, 2003)

A deep submicron power estimation methodology adaptable to variations between power characterization and estimation. - Daniel Eckerbert; Per Larsson-Edefors (ASP-DAC, 2003)

Full-custom vs. standard-cell design flow: an adder case study. - Henrik Eriksson; Per Larsson-Edefors; Tomas Henriksson; Christer Svensson (ASP-DAC, 2003)

A gate leakage reduction strategy for future CMOS circuits. - Mindaugas Drazdziulis; Per Larsson-Edefors (ESSCIRC, 2003)

A Mixed-Mode Delay-Locked-Loop Architecture. - Daniel Eckerbert; Lars J. Svensson; Per Larsson-Edefors (ICCD, 2003)

Dual Threshold Voltage Circuits in the Presence of Resistive Interconnects. - Per Larsson-Edefors; Daniel Eckerbert; Henrik Eriksson; Lars J. Svensson (ISVLSI, 2003)

A power cut-off technique for gate leakage suppression [CMOS logic circuits]. - Mindaugas Draidiiulis; Per Larsson-Edefors; Daniel Eckerbert; Henrik Eriksson (ESSCIRC, 2004)

An Efficient Twin-Precision Multiplier. - Magnus Själander; Henrik Eriksson; Per Larsson-Edefors (ICCD, 2004)

Evaluation of power cut-off techniques in the presence of gate leakage. - Mindaugas Drazdziulis; Per Larsson-Edefors (ISCAS (2), 2004)

Glitch-conscious low-power design of arithmetic circuits. - Henrik Eriksson; Per Larsson-Edefors (ISCAS (2), 2004)

Dynamic pass-transistor dot operators for efficient parallel-prefix adders. - Henrik Eriksson; Per Larsson-Edefors (ISCAS (2), 2004)

On Skin Effect in On-Chip Interconnects. - Daniel A. Andersson; Lars J. Svensson; Per Larsson-Edefors (PATMOS, 2004)

Table-Based Total Power Consumption Estimation of Memory Arrays for Architects. - Minh Quang Do; Per Larsson-Edefors; Lars Bengtsson (PATMOS, 2004)

On Maximum Current Estimation in CMOS Digital Circuits. - Dainius Ciuplys; Per Larsson-Edefors (VLSI Design, 2004)

Accounting for the skin effect during repeater insertion. - Daniel A. Andersson; Lars J. Svensson; Per Larsson-Edefors (ACM Great Lakes Symposium on VLSI, 2005)

A low-leakage twin-precision multiplier using reconfigurable power gating. - Magnus Själander; Mindaugas Drazdziulis; Per Larsson-Edefors; Henrik Eriksson (ISCAS (2), 2005)

Multiplier reduction tree with logarithmic logic depth and regular connectivity. - Henrik Eriksson; Per Larsson-Edefors; Mary Sheeran; Magnus Själander; Daniel Johansson; Martin Scholin (ISCAS, 2006)

Parameterizable Architecture-Level SRAM Power Model Using Circuit-Simulation Backend for Leakage Calibration. - Minh Quang Do; Mindaugas Drazdziulis; Per Larsson-Edefors; Lars Bengtsson (ISQED, 2006)

Toward architecture-based test-vector generation for timing verification of fast parallel multipliers. - Henrik Eriksson; Per Larsson-Edefors; Daniel Eckerbert (IEEE Trans. Very Large Scale Integr. Syst., 2006)

High-Accuracy Architecture-Level Power Estimation for Partitioned SRAM Arrays in a 65-nm CMOS BPTM Process. - Minh Quang Do; Per Larsson-Edefors; Mindaugas Drazdziulis (DSD, 2007)

Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays. - Minh Quang Do; Mindaugas Drazdziulis; Per Larsson-Edefors; Lars Bengtsson (ISQED, 2007)

Overdrive Power-Gating Techniques for Total Power Minimization. - Mindaugas Drazdziulis; Per Larsson-Edefors; Lars J. Svensson (ISVLSI, 2007)

A Flexible Datapath Interconnect for Embedded Applications. - Magnus Själander; Per Larsson-Edefors; Magnus Björk (ISVLSI, 2007)

High-speed and low-power multipliers using the Baugh-Wooley algorithm and HPM reduction tree. - Magnus Själander; Per Larsson-Edefors (ICECS, 2008)

Noise Interaction Between Power Distribution Grids and Substrate. - Daniel A. Andersson; Simon Kristiansson; Lars J. Svensson; Per Larsson-Edefors; Kjell O. Jeppson (ISQED, 2008)

Noise-Aware On-Chip Power Grid Considerations Using a Statistical Approach. - Daniel A. Andersson; Lars J. Svensson; Per Larsson-Edefors (ISQED, 2008)

Time-domain interconnect characterisation flow for appropriate model segmentation. - Daniel A. Andersson; Lars J. Svensson; Per Larsson-Edefors (IET Comput. Digit. Tech., 2008)

Custom layout strategy for rectangle-shaped log-depth multiplier reduction tree. - Patrik Kimfors; Niklas Broman; Andreas Haraldsson; Kasyab P. Subramaniyan; Magnus Själander; Henrik Eriksson; Per Larsson-Edefors (ICECS, 2009)

Layout exploration of geometrically accurate arithmetic circuits. - Kasyab P. Subramaniyan; Emil Axelsson; Per Larsson-Edefors; Mary Sheeran (ICECS, 2009)

Double Throughput Multiply-Accumulate unit for FlexCore processor enhancements. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (IPDPS, 2009)

Scheduling for an Embedded Architecture with a Flexible Datapath. - Thomas Schilling; Magnus Själander; Per Larsson-Edefors (ISVLSI, 2009)

High-speed, energy-efficient 2-cycle Multiply-Accumulate architecture. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (SoCC, 2009)

Multiplication Acceleration Through Twin Precision. - Magnus Själander; Per Larsson-Edefors (IEEE Trans. Very Large Scale Integr. Syst., 2009)

FlexCore: Utilizing Exposed Datapath Control for Efficient Computing. - Martin Thuresson; Magnus Själander; Magnus Björk; Lars J. Svensson; Per Larsson-Edefors; Per Stenström (J. Signal Process. Syst., 2009)

Design space exploration for an embedded processor with flexible datapath interconnect. - Tung Thanh Hoang; Ulf Jalmbrant; Erik der Hagopian; Kasyab P. Subramaniyan; Magnus Själander; Per Larsson-Edefors (ASAP, 2010)

Cyclic Redundancy Checking (CRC) Accelerator for the FlexCore Processor. - Muhammad Waqar Azhar; Tung Thanh Hoang; Per Larsson-Edefors (DSD, 2010)

On-chip power supply noise and its implications on timing. - Lars J. Svensson; Johnny Pihl; Daniel A. Andersson; Per Larsson-Edefors (ACM Great Lakes Symposium on VLSI, 2010)

Generation and Exploration of Layouts for Area-Efficient Barrel Shifters. - Alen Bardizbanyan; Kasyab P. Subramaniyan; Per Larsson-Edefors (ISVLSI, 2010)

A High-Speed, Energy-Efficient Two-Cycle Multiply-Accumulate (MAC) Architecture and Its Application to a Double-Throughput MAC Unit. - Tung Thanh Hoang; Magnus Själander; Per Larsson-Edefors (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

3.6-GHz 0.2-mW/ch/GHz 65-nm cross-correlator for synthetic aperture radiometry. - Erik Ryman; Anders Emrich; Stefan Back Andersson; J. Riesbeck; Lars J. Svensson; Per Larsson-Edefors (CICC, 2011)

Reconfigurable Instruction Decoding for a Wide-Control-Word Processor. - Alen Bardizbanyan; Magnus Själander; Per Larsson-Edefors (IPDPS Workshops, 2011)

Application-Specific Energy Optimization of General-Purpose Datapath Interconnect. - Babak Hidaji; Salar Alipour; Kasyab P. Subramaniyan; Per Larsson-Edefors (ISVLSI, 2011)

Viterbi Accelerator for Embedded Processor Datapaths. - Muhammad Waqar Azhar; Magnus Själander; Hasan Ali; Akshay Vijayashekar; Tung Thanh Hoang; Kashan Khurshid Ansari; Per Larsson-Edefors (ASAP, 2012)

Feasibility study of FPGA-based equalizer for 112-Gbit/s optical fiber receivers. - Fredrik Toft; Niclas Rousk; Jonas Mårtensson 002; Marco Forzati; Bengt-Erik Olsson; Per Larsson-Edefors (ISCAS, 2012)

Data-Width-Driven Power Gating of Integer Arithmetic Circuits. - Tung Thanh Hoang; Per Larsson-Edefors (ISVLSI, 2012)

Configurable RTL model for level-1 caches. - Vahid Saljooghi; Alen Bardizbanyan; Magnus Själander; Per Larsson-Edefors (NORCHIP, 2012)

Improving data access efficiency by using a tagless access buffer (TAB). - Alen Bardizbanyan; Peter Gavin; David B. Whalley; Magnus Själander; Per Larsson-Edefors; Sally A. McKee; Per Stenström (CGO, 2013)

Speculative tag access for reduced energy dissipation in set-associative L1 data caches. - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (ICCD, 2013)

A SiGe 8-channel comparator for application in a synthetic aperture radiometer. - Erik Ryman; Stefan Back Andersson; J. Riesbeck; Slavko Dejanovic; Anders Emrich; Per Larsson-Edefors (ISCAS, 2013)

Manufacturable nanometer designs using standard cells with regular layout. - Kasyab P. Subramaniyan; Per Larsson-Edefors (ISQED, 2013)

Exploring prefix-tree adders using excel spreadsheets Setting up an explorative learning environment. - Kjell O. Jeppson; Per Larsson-Edefors (MSE, 2013)

FlexCore: Implementing an exposed datapath processor. - Magnus Själander; Per Larsson-Edefors (ICSAMOS, 2013)

Designing a practical data filter cache to improve both energy efficiency and performance. - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (ACM Trans. Archit. Code Optim., 2013)

Reducing set-associative L1 data cache energy by early load data dependence detection (ELD3). - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (DATE, 2014)

Timing- and power-driven ALU design training using spreadsheet-based arithmetic exploration. - Per Larsson-Edefors; Kjell O. Jeppson (EWME, 2014)

Assessing scrubbing techniques for Xilinx SRAM-based FPGAs in space applications. - Fredrik Brosser; Emil Milh; Vilhelm Geijer; Per Larsson-Edefors (FPT, 2014)

1.6 GHz Low-Power Cross-Correlator System Enabling Geostationary Earth Orbit Aperture Synthesis. - Erik Ryman; Anders Emrich; Stefan Back Andersson; Lars J. Svensson; Per Larsson-Edefors (IEEE J. Solid State Circuits, 2014)

Energy-efficient soft-decision LDPC FEC For long-haul optical communication. - Kevin Cushon; Per Larsson-Edefors; Peter A. Andrekson (ECOC, 2015)

Impact of forward error correction on energy consumption of VCSEL-based transmitters. - Krzysztof Szczerba; Christoffer Fougstedt; Per Larsson-Edefors; Petter Westbergh; Alexandre Graell i Amat; Lars J. Svensson; Magnus Karlsson 001; Anders Larsson; Peter A. Andrekson (ECOC, 2015)

Exploring early and late ALUs for single-issue in-order pipelines. - Alen Bardizbanyan; Per Larsson-Edefors (ICCD, 2015)

Improving Data Access Efficiency by Using Context-Aware Loads and Stores. - Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (LCTES, 2015)

Redesigning a tagless access buffer to require minimal ISA changes. - Carlos Sanchez; Peter Gavin; Daniel Moreau; Magnus Själander; David B. Whalley; Per Larsson-Edefors; Sally A. McKee (CASES, 2016)

Practical way halting by speculatively accessing halt tags. - Daniel Moreau; Alen Bardizbanyan; Magnus Själander; David B. Whalley; Per Larsson-Edefors (DATE, 2016)

Logic filter cache for wide-VDD-range processors. - Alen Bardizbanyan; Oskar Andersson; Joachim Neves Rodrigues; Per Larsson-Edefors (ICECS, 2016)

Dynamic equalizer power dissipation optimization. - Christoffer Fougstedt; Pontus Johannisson; Lars J. Svensson; Per Larsson-Edefors (OFC, 2016)

Instruction level energy model for the Adapteva Epiphany multi-core processor. - Gabriel Ortiz; Lars J. Svensson; Erik Alveflo; Per Larsson-Edefors (Conf. Computing Frontiers, 2017)

Improved Low-Power LDPC FEC for Coherent Optical Systems. - Kevin Cushon; Per Larsson-Edefors; Peter A. Andrekson (ECOC, 2017)

Finite-Precision Optimization of Time-Domain Digital Back Propagation by Inter-Symbol Interference Minimization. - Christoffer Fougstedt; Lars J. Svensson; Mikael Mazur; Magnus Karlsson 001; Per Larsson-Edefors (ECOC, 2017)

A 3-GHz reconfigurable 2/3-level 96/48-channel cross-correlator for synthetic aperture radiometry. - Erik Ryman; Anders Emrich; Lars J. Svensson; Per Larsson-Edefors (ESSCIRC, 2017)

Time-domain digital back propagation: Algorithm and finite-precision implementation aspects. - Christoffer Fougstedt; Mikael Mazur; Lars J. Svensson; Henrik Eliasson; Magnus Karlsson 001; Per Larsson-Edefors (OFC, 2017)

A framework for a relative real-time tracking system based on ultra-wideband technology. - Gabriel Ortiz; Fredrik Treven; Lars J. Svensson; Per Larsson-Edefors; Sebastian Johansson-Mauricio (WPNC, 2017)

ASIC Implementation of Time-Domain Digital Backpropagation with Deep-Learned Chromatic Dispersion Filters. - Christoffer Fougstedt; Christian Häger; Lars J. Svensson; Henry D. Pfister; Per Larsson-Edefors (ECOC, 2018)

Power Consumption Savings Through Joint Carrier Recovery for Spectral and Spatial Superchannels. - Lars Lundberg; Erik Börjeson; Christoffer Fougstedt; Mikael Mazur; Magnus Karlsson 001; Peter A. Andrekson; Per Larsson-Edefors (ECOC, 2018)

A High-Throughput Low-Power Soft Bit-Flipping LDPC Decoder in 28 nm FD-SOI. - Kevin Cushon; Per Larsson-Edefors; Peter A. Andrekson (ESSCIRC, 2018)

Energy-Efficient High-Throughput Staircase Decoders. - Christoffer Fougstedt; Per Larsson-Edefors (OFC, 2018)

Custom versus Cell-Based ASIC Design for Many-Channel Correlators. - Erik Ryman; Christoffer Fougstedt; Lars J. Svensson; Per Larsson-Edefors (SiPS, 2018)

Variable-Rate FEC Decoder VLSI Architecture for 400G Rate-Adaptive Optical Communication. - Vikram Jain; Christoffer Fougstedt; Per Larsson-Edefors (ICECS, 2019)

ASIC Design Exploration of Phase Recovery Algorithms for M-QAM Fiber-Optic Systems. - Erik Börjeson; Christoffer Fougstedt; Per Larsson-Edefors (OFC, 2019)

Energy-Efficient Soft-Assisted Product Decoders. - Christoffer Fougstedt; Alireza Sheikh; Alexandre Graell i Amat; Gianluigi Liva; Per Larsson-Edefors (OFC, 2019)

Hardware Considerations for Selection Networks. - Kenneth Peter; Lars J. Svensson; Christoffer Fougstedt; Per Larsson-Edefors (VLSI-SoC, 2019)

Cycle-Slip Rate Analysis of Blind Phase Search DSP Circuit Implementations. - Erik Börjeson; Per Larsson-Edefors (OFC, 2020)

ASIC Design Exploration for DSP and FEC of 400-Gbit/s Coherent Data-Center Interconnect Receivers. - Christoffer Fougstedt; Oscar Gustafsson; Cheolyong Bae; Erik Börjeson; Per Larsson-Edefors (OFC, 2020)

Benchmarking of Carrier Phase Recovery Circuits for M-QAM Coherent Systems. - Erik Börjeson; Per Larsson-Edefors (OFC, 2021)

Variable-Rate VLSI Architecture for 400-Gb/s Hard-Decision Product Decoder. - Vikram Jain; Christoffer Fougstedt; Per Larsson-Edefors (IEEE Trans. Circuits Syst. I Regul. Pap., 2021)

Waveform Memory for Real-Time FPGA Test of Fiber-Optic Receiver DSPs. - Rafael Romón Sagredo; Erik Börjeson; Ali Mirani; Magnus Karlsson 001; Per Larsson-Edefors (NorCAS, 2022)

Fiber-on-Chip: Digital FPGA Emulation of Channel Impairments for Real-Time Evaluation of DSP. - Per Larsson-Edefors; Erik Börjeson (OFC, 2022)

Transoceanic Phase and Polarization Fiber Sensing using Real-Time Coherent Transceiver. - Mikael Mazur; Jorge C. Castellanos; Roland Ryf; Erik Börjeson; Tracy Chodkiewicz; Valey Kamalov; Shuang Yin; Nicolas K. Fontaine; Haoshuo Chen; Lauren Dallachiesa; Steve Corteselli; Philip Copping; et al. (OFC, 2022)

Real-Time Transmission over 2×55 km All 7-Core Coupled-Core Multi-Core Fiber Link. - Mikael Mazur; Lauren Dallachiesa; Nicolas K. Fontaine; Roland Ryf; Erik Börjeson; Haoshuo Chen; Hirotaka Sakuma; Takafumi Ohtsuka; Tetsuya Hayashi; Takemi Hasegawa; Hidehisa Tazawa; David T. Neilson; et al. (OFC, 2022)

Real-Time MIMO Transmission over Field-Deployed Coupled-Core Multi-Core Fibers. - Mikael Mazur; Roland Ryf; Nicolas K. Fontaine; Andrea Marotta; Erik Börjeson; Lauren Dallachiesa; Haoshuo Chen; Tetsuya Hayashi; Takuji Nagashima; Tetsuya Nakanishi; Tetsu Morishima; Fabio Graziosi; et al. (OFC, 2022)

FPGA Implementation of Multi-Layer Machine Learning Equalizer with On-Chip Training. - Keren Liu; Erik Börjeson; Christian Häger; Per Larsson-Edefors (OFC, 2023)

Field Trial of FPGA-Based Real-Time Sensing Transceiver over 524 km of Live Aerial Fiber. - Mikael Mazur; Dennis Wallberg; Lauren Dallachiesa; Erik Börjeson; Roland Ryf; Magnus Bergroth; Börje Josefsson; Nicolas K. Fontaine; Haoshuo Chen; David T. Neilson; Jochen Schröder; Per Larsson-Edefors; et al. (OFC, 2023)

Unfolded SiBM BCH Decoders for High- Throughput Low-Latency Applications. - Xu Wang; Christoffer Fougstedt; Lars J. Svensson; Per Larsson-Edefors (ISVLSI, 2024)

Circuit Implementation of Pilot-Based Dynamic MIMO Equalization for Coupled-Core Fibers. - Erik Börjeson; Ekaterina Deriushkina; Mikael Mazur; Magnus Karlsson 001; Per Larsson-Edefors (OFC, 2024)

Real-Time Implementation of Machine-Learning DSP. - Erik Börjeson; Keren Liu; Christian Häger; Per Larsson-Edefors (OFC, 2024)

Real-Time Monitoring of Cable Break in a Live Network using a Coherent Transceiver Prototype. - Mikael Mazur; Dennis Wallberg; Lauren Dallachiesa; Erik Börjeson; Roland Ryf; Magnus Bergroth; Börje Josefsson; Nicolas K. Fontaine; Haoshuo Chen; David T. Neilson; Jochen Schröder; Per Larsson-Edefors; et al. (OFC, 2024)

Implementation Evaluation of Fixed-Point Multipliers for Complex Numbers. - Per Larsson-Edefors; Erik Börjeson (ARITH, 2025)

Low-Power Complex Multiplier Pin Assignment Based on Spatial and Temporal Signal Properties. - Per Larsson-Edefors; Erik Börjeson (ISCAS, 2025)

FPGA-Based Wordlength Optimization for DSP. - Chenhao Yang; Jinsheng Bian; Erik Börjeson; Per Larsson-Edefors (ISCAS, 2025)

Activity-Based Input Operand Assignment for Reduced Multiplier Power Dissipation. - Per Larsson-Edefors; Erik Börjeson (LASCAS, 2025)