A 1-V 128-kb four-way set-associative CMOS cache memory using wordline-oriented tag-compare (WLOTC) structure with the content-addressable-memory (CAM) 10-transistor tag cell. - Perng-Fei Lin; James B. Kuo (IEEE J. Solid State Circuits, 2001)

A 0.8-V 128-kb four-way set-associative two-level CMOS cache memory using two-stage wordline/bitline-oriented tag-compare (WLOTC/BLOTC) scheme. - Perng-Fei Lin; James B. Kuo (IEEE J. Solid State Circuits, 2002)