Register Renaming and Scheduling for Dynamic Execution of Predicated Code. - Perry H. Wang; Hong Wang 003; Ralph-Michael Kling; Kalpana Ramakrishnan; John Paul Shen (HPCA, 2001)

Quantitative Evaluation of the Register Stack Engine and Optimizations for Future Itanium Processors. - R. David Weldon; Steven S. Chang; Hong Wang 003; Gerolf Hoflehner; Perry H. Wang; Daniel M. Lavery; John Paul Shen (Interaction between Compilers and Computer Architectures, 2002)

Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation. - Perry H. Wang; Hong Wang 003; Jamison D. Collins; Ed Grochowski; Ralph-Michael Kling; John Paul Shen (HPCA, 2002)

Post-Pass Binary Adaptation for Software-Based Speculative Precomputation. - Shih-Wei Liao; Perry H. Wang; Hong Wang 003; John Paul Shen; Gerolf Hoflehner; Daniel M. Lavery (PLDI, 2002)

Inferno: a functional simulation infrastructure for modeling microarchitectural data speculations. - Hong Wang 003; Shiri Manor; Dave LaFollette; Nadav Nesher; Ku-jei King; Perry H. Wang; Shay Levy; Shai Satt; Gal Carmeli; Arjun Kapur; Ioannis Schoinas; Ed Rubinstein; et al. (ISPASS, 2003)

Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (ASPLOS, 2004)

Physical Experimentation with Prefetching Helper Threads on Intel's Hyper-Threaded Processors. - Dongkeun Kim; Shih-Wei Liao; Perry H. Wang; Juan del Cuvillo; Xinmin Tian; Xiang Zou; Hong Wang 003; Donald Yeung; Milind Girkar; John Paul Shen (CGO, 2004)

Helper Threads via Virtual Multithreading. - Perry H. Wang; Jamison D. Collins; Hong Wang 003; Dongkeun Kim; Bill Greene; Kai-Ming Chan; Aamir B. Yunus; Terry Sych; Stephen F. Moore; John Paul Shen (IEEE Micro, 2004)

A Dependency Chain Clustered Microarchitecture. - Satish Narayanasamy; Hong Wang 003; Perry H. Wang; John Paul Shen; Brad Calder (IPDPS, 2005)

Multiple Instruction Stream Processor. - Richard A. Hankins; Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Ryan N. Rakvic; Hong Wang 003; John Paul Shen (ISCA, 2006)

Sequencer virtualization. - Perry H. Wang; Jamison D. Collins; Gautham N. Chinya; Bernard Lint; Asit Mallick; Koichi Yamada; Hong Wang 003 (ICS, 2007)

EXOCHI: architecture and programming environment for a heterogeneous multi-core multithreaded system. - Perry H. Wang; Jamison D. Collins; Gautham N. Chinya; Hong Jiang; Xinmin Tian; Milind Girkar; Nick Y. Yang; Guei-Yuan Lueh; Hong Wang 003 (PLDI, 2007)

Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. - Henry Wong; Anne Bracy; Ethan Schuchman; Tor M. Aamodt; Jamison D. Collins; Perry H. Wang; Gautham N. Chinya; Ankur Khandelwal Groen; Hong Jiang; Hong Wang 003 (PACT, 2008)

Intel® atomTM processor core made FPGA-synthesizable. - Perry H. Wang; Jamison D. Collins; Christopher T. Weaver; Belliappa Kuttanna; Shahram Salamian; Gautham N. Chinya; Ethan Schuchman; Oliver Schilling; Thorsten Doil; Sebastian Steibl; Hong Wang 003 (FPGA, 2009)

Intel nehalem processor core made FPGA synthesizable. - Graham Schelle; Jamison D. Collins; Ethan Schuchman; Perry H. Wang; Xiang Zou; Gautham N. Chinya; Ralf Plate; Thorsten Mattner; Franz Olbrich; Per Hammarlund; Ronak Singhal; Jim Brayton; et al. (FPGA, 2010)

Bothnia: a dual-personality extension to the Intel integrated graphics driver. - Gautham N. Chinya; Jamison D. Collins; Perry H. Wang; Hong Jiang; Guei-Yuan Lueh; Thomas Piazza; Hong Wang 003 (ACM SIGOPS Oper. Syst. Rev., 2011)

7.1 A 3.4-to-13.3TOPS/W 3.6TOPS Dual-Core Deep-Learning Accelerator for Versatile AI Applications in 7nm 5G Smartphone SoC. - Chien-Hung Lin; Chih-Chung Cheng; Yi-Min Tsai; Sheng-Je Hung; Yu-Ting Kuo; Perry H. Wang; Pei-Kuei Tsung; Jeng-Yun Hsu; Wei-Chih Lai; Chia-Hung Liu; Shao-Yu Wang; Chin-Hua Kuo; et al. (ISSCC, 2020)

tubGEMM: Energy-Efficient and Sparsity-Effective Temporal-Unary-Binary Based Matrix Multiply Unit. - Prabhu Vellaisamy; Harideep Nair; Joseph Finn; Manav Trivedi; Albert Chen 002; Anna Li; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (ISVLSI, 2023)

Commercial Evaluation of Zero-Skipping MAC Design for Bit Sparsity Exploitation in DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (VLSI-SoC, 2024)

OzMAC: An Energy-Efficient Sparsity-Exploiting Multiply-Accumulate-Unit Design for DL Inference. - Harideep Nair; Prabhu Vellaisamy; Tsung-Han Lin; Perry H. Wang; Ronald Shawn Blanton; John Paul Shen (CoRR, 2024)