Multi band sigma delta analog to digital conversion. - Pervez M. Aziz; Henrik V. Sorensen; Jan Van der Spiegel (ICASSP (3), 1994)

Performance of Complex Noise Transfer Functions in Bandpass and Multi Band Sigma Delta Systems. - Pervez M. Aziz; Henrik V. Sorensen; Jan Van der Spiegel (ISCAS, 1995)

An overview of sigma-delta converters. - Pervez M. Aziz; Henrik V. Sorensen; Jan Van der Spiegel (IEEE Signal Process. Mag., 1996)

A rate 16/17 punctured MTR block code. - Pervez M. Aziz; Necip Sayiner; Viswanath Annampedu (ICC, 1999)

Symbol rate timing recovery for higher order partial response channels. - Pervez M. Aziz; Srinivasan Surendran (IEEE J. Sel. Areas Commun., 2001)

Adaptation algorithms for a class of continuous time analog equalizers with application to serial links. - Pervez M. Aziz; Amaresh V. Malipatil (ISCAS, 2011)

A 1.0625-to-14.025Gb/s multimedia transceiver with full-rate source-series-terminated transmit driver and floating-tap decision-feedback equalizer in 40nm CMOS. - Shaolei Quan; Freeman Zhong; Wing Liu; Pervez M. Aziz; Tai Jing; Jen Dong; Chintan Desai; Hairong Gao; Monica Garcia; Gary Hom; Tony Huynh; Hiroshi Kimura; et al. (ISSCC, 2011)

A 1.0625 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS. - Freeman Zhong; Shaolei Quan; Wing Liu; Pervez M. Aziz; Tai Jing; Jen Dong; Chintan Desai; Hairong Gao; Monica Garcia; Gary Hom; Tony Huynh; Hiroshi Kimura; et al. (IEEE J. Solid State Circuits, 2011)

A class of downsampled floating tap DFE architectures with application to serial links. - Pervez M. Aziz; Hiroshi Kimura; Amaresh V. Malipatil; Shiva Kotagiri (ISCAS, 2012)

Analysis of a class of decimated clock/data recovery architectures for serial links. - Pervez M. Aziz; Amaresh V. Malipatil (ISCAS, 2013)

Shift register multi-phase clock based downsampled floating tap DFE for serial links. - Pervez M. Aziz; Hiroshi Kimura; Amaresh V. Malipatil; Shiva Kotagiri; Gordon Chan; Hairong Gao (ISCAS, 2014)

2.1 28Gb/s 560mW multi-standard SerDes with single-stage analog front-end and 14-tap decision-feedback equalizer in 28nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; Ruchi Kothari; et al. (ISSCC, 2014)

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS. - Hiroshi Kimura; Pervez M. Aziz; Tai Jing; Ashutosh Sinha; Shiva Prasad Kotagiri; Ram Narayan; Hairong Gao; Ping Jing; Gary Hom; Anshi Liang; Eric Zhang; Aniket Kadkol; et al. (IEEE J. Solid State Circuits, 2014)