Peter Harrod
Orcid: 0000-0002-8857-3369
According to our database1,
Peter Harrod
authored at least 20 papers
between 1993 and 2021.
Collaborative distances:
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Bibliography
2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2018
Addressing Functional Safety Challenges in Autonomous Vehicles with the Arm TCL S Architecture.
IEEE Des. Test, 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
2013
Proceedings of the 18th IEEE European Test Symposium, 2013
2010
Gate-Sizing-Based Single V<sub>dd</sub> Test for Bridge Defects in Multivoltage Designs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010
2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009
Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing.
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 17th IEEE Asian Test Symposium, 2008
2007
Proceedings of the 16th Asian Test Symposium, 2007
2006
Proceedings of the 11th European Test Symposium, 2006
2003
The P1500 DFT Disclosure Document: A Standard to Communicate Mergeable Core DFT Data.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003
2000
1999
Test in the Emerging Intellectual Property Business.
IEEE Des. Test Comput., 1999
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999
1993
Microprocess. Microsystems, 1993