JHDL - An HDL for Reconfigurable Systems. - Peter Bellows; Brad L. Hutchings (FCCM, 1998)

A CAD Suite for High-Performance FPGA Design. - Brad L. Hutchings; Peter Bellows; Joseph Hawkins; K. Scott Hemmert; Brent E. Nelson; Mike Rytting (FCCM, 1999)

Experimental Testing of the Gigabit IPSec-Compliant Implementations of Rijndael and Triple DES Using SLAAC-1V FPGA Accelerator Board. - Pawel Chodowiec; Kris Gaj; Peter Bellows; Brian Schott (ISC, 2001)

Designing Run-Time Reconfigurable Systems with JHDL. - Peter Bellows; Brad L. Hutchings (J. VLSI Signal Process., 2001)

GRIP: A Reconfigurable Architecture for Host-Based Gigabit-Rate Packet Processing. - Peter Bellows; Jaroslav Flidr; Tom Lehman; Brian Schott; Keith D. Underwood (FCCM, 2002)

Comparative Analysis of the Hardware Implementations of Hash Functions SHA-1 and SHA-512. - Tim Grembowski; Roar Lien; Kris Gaj; Nghi Nguyen; Peter Bellows; Jaroslav Flidr; Tom Lehman; Brian Schott (ISC, 2002)

Applications of adaptive computing systems for signal processing challenges. - Brian Schott; Peter Bellows; Matthew French; Robert Parker (ASP-DAC, 2003)

IPsec-Protected Transport of HDTV over IP. - Peter Bellows; Jaroslav Flidr; Ladan Gharai; Colin Perkins; Pawel Chodowiec; Kris Gaj (FPL, 2003)

Distinguished Paper: High-Visibility Debug-by-Design for FPGA Platforms. - Peter Bellows (ERSA, 2004)

High-Visibility Debug-By-Design for FPGA Platforms. - Peter Bellows (J. Supercomput., 2005)