GaAs Komponenten der Integrierten Optik für die externe Modulation in optischen Kommunikationssystemen. - Peter Buchmann (1987)

Reproduction of Hypermedia Lectures. - Albert Geukes; Peter Buchmann (WebNet, 1998)

Design Methodology for a Large Communication Chip. - Rolf Clauberg; Peter Buchmann; Andreas Herkersdorf; David J. Webb (IEEE Des. Test Comput., 2000)

Single-chip 622-Mb/s SDH/SONET framer, digital cross-connect and add/drop multiplexer solution. - Peter H. Baechtold; Michael P. Beakes; Peter Buchmann; Rolf Clauberg; John F. Ewen; John F. Gilsdorf; Philippe Hauviller; Andreas Herkersdorf; Jean-Claude Le Garrec; Wolfram W. Lemppenau; Ben Parker; Dale J. Pearson; et al. (IEEE J. Solid State Circuits, 2001)

A 0.94-ps-RMS-jitter 0.016-mm2 2.5-GHz multiphase generator PLL with 360° digitally programmable phase shift for 10-Gb/s serial links. - Thomas Toifl; Christian Menolfi; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Robert Reutemann; Michael Ruegg; Martin L. Schmatz; Jonas R. M. Weiss (IEEE J. Solid State Circuits, 2005)

A 22-gb/s PAM-4 receiver in 90-nm CMOS SOI technology. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Jonas R. M. Weiss; Martin L. Schmatz (IEEE J. Solid State Circuits, 2006)

A 16Gb/s Source-Series Terminated Transmitter in 65nm CMOS SOI. - Christian Menolfi; Thomas Toifl; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Jonas R. M. Weiss; Martin L. Schmatz (ISSCC, 2007)

A 72mW 0.03mm2 Inductorless 40Gb/s CDR in 65nm SOI CMOS. - Thomas Toifl; Christian Menolfi; Peter Buchmann; Christoph Hagleitner; Marcel A. Kossel; Thomas Morf; Jonas R. M. Weiss; Martin L. Schmatz (ISSCC, 2007)

A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS. - Marcel A. Kossel; Christian Menolfi; Jonas R. M. Weiss; Peter Buchmann; George von Büren; Lucio Rodoni; Thomas Morf; Thomas Toifl; Martin L. Schmatz (ISSCC, 2008)

A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth. - Marcel A. Kossel; Christian Menolfi; Jonas R. M. Weiss; Peter Buchmann; George von Büren; Lucio Rodoni; Thomas Morf; Thomas Toifl; Martin L. Schmatz (IEEE J. Solid State Circuits, 2008)

LC PLL With 1.2-Octave Locking Range Based on Mutual-Inductance Switching in 45-nm SOI CMOS. - Marcel A. Kossel; Thomas Morf; Jonas R. M. Weiss; Peter Buchmann; Christian Menolfi; Thomas Toifl; Martin L. Schmatz (IEEE J. Solid State Circuits, 2009)

A 1.25-5 GHz Clock Generator With High-Bandwidth Supply-Rejection Using a Regulated-Replica Regulator in 45-nm CMOS. - Thomas Toifl; Christian Menolfi; Peter Buchmann; Marcel A. Kossel; Thomas Morf; Martin L. Schmatz (IEEE J. Solid State Circuits, 2009)

A 14Gb/s high-swing thin-oxide device SST TX in 45nm CMOS SOI. - Christian Menolfi; Thomas Toifl; Michael Ruegg; Matthias Braendli; Peter Buchmann; Marcel A. Kossel; Thomas Morf (ISSCC, 2011)

A 28Gb/s source-series terminated TX in 32nm CMOS SOI. - Christian Menolfi; Juergen Hertle; Thomas Toifl; Thomas Morf; Daniele Gardellini; Matthias Braendli; Peter Buchmann; Marcel A. Kossel (ISSCC, 2012)

A 3.1mW/Gbps 30Gbps quarter-rate triple-speculation 15-tap SC-DFE RX data path in 32nm CMOS. - Thomas Toifl; Michael Ruegg; Rajesh Inti; Christian Menolfi; Matthias Braendli; Marcel A. Kossel; Peter Buchmann; Pier Andrea Francese; Thomas Morf (VLSIC, 2012)

A 28-Gb/s 4-Tap FFE/15-Tap DFE Serial Link Transceiver in 32-nm SOI CMOS Technology. - John F. Bulzacchelli; Christian Menolfi; Troy J. Beukema; Daniel W. Storaska; Juergen Hertle; David Hanson; Ping-Hsuan Hsieh; Sergey V. Rylov; Daniel Furrer; Daniele Gardellini; Andrea Prati 002; Thomas Morf; et al. (IEEE J. Solid State Circuits, 2012)

A 2.6 mW/Gbps 12.5 Gbps RX With 8-Tap Switched-Capacitor DFE in 32 nm CMOS. - Thomas Toifl; Christian Menolfi; Michael Ruegg; Robert Reutemann; Daniel Dreps; Troy J. Beukema; Andrea Prati 002; Daniele Gardellini; Marcel A. Kossel; Peter Buchmann; Matthias Braendli; Pier Andrea Francese; et al. (IEEE J. Solid State Circuits, 2012)

A 5.7mW/Gb/s 24-to-240Ω 1.6Gb/s thin-oxide DDR transmitter with 1.9-to-7.6V/ns clock-feathering slew-rate control in 22nm CMOS. - Marcel A. Kossel; Christian Menolfi; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Peter Buchmann; Lukas Kull; Toke Meyer Andersen; Thomas Morf (ISSCC, 2013)

An 8Gb/s 1.5mW/Gb/s 8-tap 6b NRZ/PAM-4 Tomlinson-Harashima precoding transmitter for future memory-link applications in 22nm CMOS. - Marcel A. Kossel; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Christian Menolfi; Peter Buchmann; Lukas Kull; Toke Meyer Andersen; Thomas Morf (ISSCC, 2013)

A 10 Gb/s 8-Tap 6b 2-PAM/4-PAM Tomlinson-Harashima Precoding Transmitter for Future Memory-Link Applications in 22-nm SOI CMOS. - Marcel A. Kossel; Thomas Toifl; Pier Andrea Francese; Matthias Braendli; Christian Menolfi; Peter Buchmann; Lukas Kull; Toke Meyer Andersen; Thomas Morf (IEEE J. Solid State Circuits, 2013)

A 16 Gb/s receiver with DC wander compensated rail-to-rail AC coupling and passive linear-equalizer in 22 nm CMOS. - Pier Andrea Francese; Thomas Toifl; Matthias Braendli; Peter Buchmann; Thomas Morf; Marcel A. Kossel; Christian Menolfi; Lukas Kull; Toke Meyer Andersen; Hazar Yueksel (ESSCIRC, 2014)

A 3.5pJ/bit 8-tap-feed-forward 8-tap-decision feedback digital equalizer for 16Gb/s I/Os. - Thomas Toifl; Peter Buchmann; Troy J. Beukema; Michael P. Beakes; Matthias Braendli; Pier Andrea Francese; Christian Menolfi; Marcel A. Kossel; Lukas Kull; Thomas Morf (ESSCIRC, 2014)

Scalable, efficient ASICS for the square kilometre array: From A/D conversion to central correlation. - Martin L. Schmatz; Rik Jongerius; Gero Dittmann; Andreea Anghel; Ton Engbersen; Jan van Lunteren; Peter Buchmann (ICASSP, 2014)

4.7 A sub-ns response on-chip switched-capacitor DC-DC voltage regulator delivering 3.7W/mm2 at 90% efficiency using deep-trench capacitors in 32nm SOI CMOS. - Toke Meyer Andersen; Florian Krismer; Johann W. Kolar; Thomas Toifl; Christian Menolfi; Lukas Kull; Thomas Morf; Marcel A. Kossel; Matthias Braendli; Peter Buchmann; Pier Andrea Francese (ISSCC, 2014)

A 16 Gb/s 3.7 mW/Gb/s 8-Tap DFE Receiver and Baud-Rate CDR With 31 kppm Tracking Bandwidth. - Pier Andrea Francese; Thomas Toifl; Peter Buchmann; Matthias Braendli; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Lukas Kull; Toke Meyer Andersen (IEEE J. Solid State Circuits, 2014)

A 3.6pJ/b 56Gb/s 4-PAM receiver with 6-Bit TI-SAR ADC and quarter-rate speculative 2-tap DFE in 32 nm CMOS. - Hazar Yueksel; Lukas Kull; Andreas Burg 001; Matthias Braendli; Peter Buchmann; Pier Andrea Francese; Christian Menolfi; Marcel A. Kossel; Thomas Morf; Toke Meyer Andersen; Danny Luu; Thomas Toifl (ESSCIRC, 2015)

3.1 A 25Gb/s ADC-based serial line receiver in 32nm CMOS SOI. - Sergey V. Rylov; Troy J. Beukema; Zeynep Toprak Deniz; Thomas Toifl; Yong Liu 023; Ankur Agrawal; Peter Buchmann; Alexander V. Rylyakov; Michael P. Beakes; Benjamin D. Parker; Mounir Meghelli (ISSCC, 2016)