5.5 V tolerant I/O in a 2.5 V 0.25 μm CMOS technology. - Anne-Johan Annema; Govert Geelen; Peter C. de Jong (CICC, 2000)

5.5-V I/O in a 2.5-V 0.25-μm CMOS technology. - Anne-Johan Annema; Govert J. G. M. Geelen; Peter C. de Jong (IEEE J. Solid State Circuits, 2001)

A 3-D Circuit Model to evaluate CDM performance of ICs. - M. S. B. Sowariraj; Theo Smedes; Peter C. de Jong; Cora Salm; Ton J. Mouthaan; Fred G. Kuper (Microelectron. Reliab., 2005)

ESD robust high-voltage active clamps. - Guido Notermans; Olivier Quittard; Anco Heringa; Zeljko Mrcarica; Fabrice Blanc; Hans van Zwol; Theo Smedes; Thomas Keller 004; Peter C. de Jong (Microelectron. Reliab., 2009)

ESD protection for thin gate oxides in 65 nm. - Guido Notermans; Theo Smedes; Zeljko Mrcarica; Peter C. de Jong; Ralph Stephan; Hans van Zwol; Dejan M. Maksimovic (Microelectron. Reliab., 2010)